DSP-Based Modular Multiplication for Low-Latency Blockchain
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Solution Overview
Problem
Existing modular multiplication algorithms for decentralized blockchains, particularly in cryptography, face challenges with high latency and resource-intensive logic circuits due to the complexity of modular exponentiation with large integers, which is exacerbated by the need for low-latency implementations and the limitations of field programmable gate array (FPGA) multiplier circuits.
Innovation Solution
The solution involves a modular multiplication method using digital signal processing (DSP) blocks and adders to perform column-based additions and multiplicative expansions, reducing the need for large multiplier circuits and lookup tables, thereby decreasing latency and resource usage while increasing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional modular multiplication algorithms are used for decentralized blockchains, then cryptographic security is maintained, but latency increases and resource consumption increases
Solution Approach 1:
The patent segments the modular multiplication operation into distinct phases: multiplicative expansion phase and modular reduction phase. The multiplicative expansion uses DSP blocks to compute partial products, while the modular reduction uses a separate circuit structure. This segmentation allows each phase to be optimized independently, reducing overall latency while maintaining cryptographic security through the complete modular multiplication process.
Solution Approach 2:
The patent transitions from traditional sequential modular multiplication to a parallel processing approach by using DSP blocks arranged in multiple rows and columns. The modular reduction circuit processes multiple bits simultaneously through column-based addition structures. This dimensional change from sequential to parallel processing significantly reduces latency while preserving the mathematical correctness of the cryptographic operation.
2Reliability
If traditional modular multiplication algorithms are used for decentralized blockchains, then cryptographic security is maintained, but resource consumption increases
Solution Approach 1:
The patent divides the resource-intensive modular multiplication into two separate circuit structures: a multiplicative expansion structure using DSP blocks and a modular reduction structure using column-based adders. This segmentation allows resources to be allocated efficiently to each phase, reducing overall resource consumption while maintaining the security requirements of complete modular multiplication for cryptographic applications.
Solution Approach 2:
The patent replaces traditional mechanical-style sequential multiplication circuits with signal processing-oriented DSP blocks and parallel addition structures. The DSP blocks perform multiplicative expansion through optimized signal processing operations, and the modular reduction uses column-based addition instead of traditional subtraction-based methods. This substitution reduces resource consumption by leveraging the inherent parallelism and efficiency of signal processing hardware.
3Loss of time
If DSP blocks and adders are used for modular multiplication, then latency is reduced and resource consumption is reduced, but circuit complexity increases
Solution Approach 1:
The patent creates a universal modular multiplication circuit that can handle different input sizes and cryptographic parameters through configurable DSP block arrangements and scalable column-based addition structures. The same basic circuit architecture can be adapted for various modular multiplication requirements, reducing the need for multiple specialized circuits and thereby managing complexity while maintaining low latency performance across different applications.
4Reliability
If FPGA multiplier circuits are used for modular exponentiation with large integers, then cryptographic operations can be performed, but latency increases and resource usage increases
Solution Approach 1:
The patent segments the modular exponentiation operation into multiple modular multiplication steps, where each step uses the optimized DSP-based multiplicative expansion and column-based modular reduction. This segmentation allows the exponentiation to be performed as a sequence of optimized multiplications rather than a single resource-intensive operation, reducing overall latency while maintaining the capability to handle large integers required for cryptographic security.
Solution Approach 2:
The patent transitions from traditional FPGA multiplier circuit architecture to a signal processing dimension using DSP blocks and column-based addition structures. This dimensional change enables parallel processing of multiple bits simultaneously, significantly reducing the latency of modular exponentiation with large integers while preserving the cryptographic operation capability through mathematically equivalent transformations.
Data Source
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Figure 3A~3B
AI summary
A circuit system for performing modular reduction of a modular multiplication includes multiplier circuits that receive a first subset of coefficients that are generated by summing partial products of a multiplication operation that is part of the modular multiplication. The multiplier circuits multiply the coefficients in the first subset by constants that equal remainders of divisions to generate products. Adder circuits add a second subset of the coefficients and segments of bits of the products that are aligned with respective ones of the second subset of the coefficients to generate sums.