18×18 DSP Multiplier Reuse for Parallel Low-Bit Multiplications
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Solution Overview
Problem
Conventional programmable logic devices (PLDs) with specialized processing blocks, such as digital signal processing (DSP) blocks, are limited by the capability of their multipliers, specifically 18×18 multipliers, which can only support a single 8×8 multiplication operation, failing to meet the higher density multiplication requirements of recent artificial intelligence applications like machine learning and deep learning that necessitate multiple smaller precision multiplications.
Innovation Solution
Configuring an 18×18 multiplier to support multiple smaller multiplications, such as two 8×8 multiplications, by using soft logic to correct potential errors and decomposing operations, allowing for the extraction of multiple sub-multipliers from a single larger multiplier, thereby improving computational and power density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single 18×18 multiplier is used, then device complexity is reduced, but multiplication density (number of simultaneous multiplications) is limited to one
Solution Approach 1:
The patent segments the 18×18 multiplier operations into multiple independent 8×8 sub-multiplier operations. By dividing the multiplication task into smaller segments that can be executed in parallel, the system achieves higher multiplication density while using a single physical multiplier unit, thereby resolving the contradiction between productivity and device complexity.
Solution Approach 2:
The patent implements dynamic configuration of the multiplier circuit to support multiple operational modes. The same 18×18 multiplier hardware can be dynamically reconfigured to perform different numbers and sizes of multiplications based on computational requirements, enabling high multiplication density without increasing physical device complexity.
2Productivity
If multiple separate 8×8 multipliers are implemented, then multiplication density increases, but power consumption and cost increase
Solution Approach 1:
The patent merges multiple 8×8 multiplier functions into a single 18×18 multiplier unit. By combining what would traditionally require separate hardware instances into one shared resource, the system achieves high multiplication density while reducing overall power consumption and implementation cost, directly addressing the contradiction between productivity and energy usage.
Solution Approach 2:
The 18×18 multiplier is designed as a universal computing resource that can perform multiple 8×8 multiplications through software-controlled configuration. This multi-functionality allows a single hardware unit to replace multiple dedicated multipliers, reducing power consumption while maintaining high multiplication density for AI workloads.
3Productivity
If an 18×18 multiplier is configured for multiple 8×8 multiplications, then computational density improves, but manufacturing precision requirements increase due to bit correction needs
Solution Approach 1:
The patent incorporates feedback mechanisms through correction logic that monitors and adjusts the output of sub-multiplier operations. By implementing feedback-based error correction, the system can achieve high computational density while maintaining the necessary manufacturing precision, as the correction logic compensates for any precision losses in the segmented multiplication process.
Solution Approach 2:
The patent introduces intermediary correction logic and control circuits that mediate between the segmented multiplication operations and the final result. These intermediary components ensure that bit-level precision is maintained throughout the multiple 8×8 multiplication process, resolving the contradiction between computational density and manufacturing precision requirements.
Data Source
AI summary
Integrated circuits with digital signal processing (DSP) blocks are provided. A DSP block may include one or more large multiplier circuits. A large multiplier circuit such as an 18×18 multiplier circuit may be used to support two or more smaller multiplication operations such as two 8×8 integer multiplications or two 9×9 integer multiplications. To implement the two 8×8 or 9×9 unsigned/signed multiplications, the 18×18 multiplier may be configured to support two 8×8 multiplications with one shared operand, two 6×6 multiplications without any shared operand, or two 7×7 multiplications without any shared operand. Any potential overlap of partial product terms may be subtracted out using correction logic. The multiplication of the remaining most significant bits can be computed using associated multiplier extension logic and appended to the other least significant bits using merging logic.