DSP Multiplier Circuit Segmentation for AI Workloads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional digital signal processing (DSP) blocks in programmable logic devices face challenges in supporting high-density multiplication operations required by recent advancements in artificial intelligence, particularly in machine learning and deep learning, which demand more efficient handling of smaller precision multiplications such as 3×3, 4×4, and 6×6 operations without overcomplicating the block design.
Innovation Solution
The solution involves extracting multiple smaller multipliers from a larger 18×18 multiplier within a programmable integrated circuit, allowing for efficient support of various multiplication operations by configuring the inputs and outputs to accommodate different sizes of multiplications, such as 6×6, 4×4, and 2×2, while mitigating overflow issues through strategic bit configuration and correction techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional DSP block uses two 18×18 multipliers to support IEEE 754 single precision floating-point multiplication, then it achieves 23 bits of precision, but it cannot efficiently support high-density smaller precision multiplications required by AI workloads
Solution Approach 1:
The patent divides a single large multiplier (e.g., 18×18 or 36×36) into multiple smaller multipliers (e.g., four 6×6 multipliers) by segmenting the input bit ranges. Each smaller multiplier operates on specific bit portions of the inputs, allowing parallel execution of multiple small precision multiplications required by AI workloads like matrix operations.
Solution Approach 2:
The patent makes the multiplier circuit universal by enabling it to perform both large precision multiplications (for traditional DSP applications) and multiple small precision multiplications (for AI workloads) using the same hardware resource. Configuration controls allow the circuit to adapt its function based on the computational requirements.
2Productivity
If the multiplier is configured to support multiple smaller multiplications, then functional density increases, but overflow issues arise from interactions between parallel multiplication operations
Solution Approach 1:
The patent applies preliminary anti-action by pre-calculating the number of set bits (population count) in specific input bit ranges and using this information to determine whether overflow will occur. This allows the circuit to preemptively identify and correct overflow conditions before they propagate errors, ensuring reliability while maintaining high functional density.
Solution Approach 2:
The patent implements feedback mechanisms where the results of parallel multiplication operations are monitored for overflow conditions. When overflow is detected in one operation, the circuit adjusts or corrects results from other operations accordingly, ensuring that the final computational output remains accurate despite the parallel processing of multiple multiplications.
3Adaptability or versatility
If additional circuitry is added to support multiple multiplication modes, then versatility for AI workloads improves, but the block design becomes overly complicated
Solution Approach 1:
The patent merges multiple multiplication operations into a single unified circuit structure. Instead of implementing separate multiplier circuits for different precision requirements, the design combines four 6×6 multipliers within a single 18×18 or 36×36 multiplier framework, sharing common resources and control logic to reduce overall complexity while maintaining versatility.
Solution Approach 2:
The patent introduces dynamic configuration capabilities that allow the multiplier circuit to adapt its operation mode based on computational requirements. Configuration controls enable the circuit to switch between supporting single large precision multiplication or multiple small precision multiplications, providing versatility without requiring multiple fixed dedicated circuits.
Data Source
AI summary
Integrated circuits with digital signal processing (DSP) blocks are provided. A DSP block may include one or more large multiplier circuits. A large multiplier circuit (e.g., an 18×18 or 18×19 multiplier circuit) may be used to support two or more smaller multiplication operations sharing one or two sets of multiplier operands, a complex multiplication, and a sum of two multiplications. If the multiplier products overflow and interfere with one another, correction operations can be performed. Partial products from two or more larger multiplier circuits can be used to combine decomposed partial products. A large multiplier circuit can also be used to support two floating-point mantissa multipliers.