DSP Block Multiplier Arrays for Tensor Processing
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Solution Overview
Problem
Current integrated circuit devices face challenges in performing both digital signal processing and machine learning tasks efficiently, as circuitry optimized for one application often lacks the necessary capabilities for the other, leading to suboptimal performance and resource utilization.
Innovation Solution
The development of a digital signal processing (DSP) block on an integrated circuit device that can perform multiply-accumulate operations, utilizing field-programmable gate arrays (FPGAs) to adapt to emerging algorithms and support both fixed-point and floating-point arithmetic, enabling efficient processing for both digital signal processing and machine learning applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If circuitry is optimized for digital signal processing, then digital signal processing performance is improved, but machine learning capability deteriorates
Solution Approach 1:
The DSP block is designed to perform multiple functions including both digital signal processing operations (multiply, accumulate, add) and machine learning operations (matrix multiplication, convolution). By making the circuitry universal, it can be configured through programmable logic to execute different algorithms and workloads, thereby improving both DSP performance and ML capability without requiring separate dedicated hardware for each function type.
2Productivity
If circuitry is optimized for machine learning, then machine learning performance is improved, but digital signal processing capability deteriorates
Solution Approach 1:
The same DSP block that enables machine learning operations through programmable logic also maintains full digital signal processing capability. The block can be dynamically reconfigured via HDL code to perform traditional DSP tasks such as filtering, Fourier transforms, and signal modulation, ensuring that ML optimization does not come at the expense of DSP functionality.
3Productivity
If large multipliers are implemented in tensor arrays, then machine learning computation capability is improved, but area cost increases
Solution Approach 1:
Large multipliers are decomposed into multiple smaller multiplier blocks arranged in arrays. Each small multiplier handles a portion of the computation, and their results are combined through adder trees. This segmentation reduces the area footprint of individual multiplier units while achieving the same overall computational capability through parallel processing across multiple units.
Solution Approach 2:
Instead of implementing a single large multiplier that would consume significant area, the design transitions to a two-dimensional array of smaller multipliers. This dimensional transformation allows the computation to be distributed across space (multiple small units) rather than concentrated in a single large unit, thereby reducing peak area requirements while maintaining computational throughput.
Data Source
AI summary
The present disclosure describes an integrated circuit device that includes a digital signal processing (DSP) block. The DSP block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Also, the first plurality of inputs, the second plurality of inputs, or both are derived from higher precision values. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.