Digital Signal Processor for Optical Receivers Using Segmented Equalization

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Solution Overview

Problem

In digital coherent optical receivers, achieving high signal quality is hindered by the difficulty in compensating for different types of waveform distortion, particularly unknown static and dynamic distortions, due to limitations in circuit size and equalization performance, leading to suboptimal performance in demodulated signals.

Innovation Solution

A digital signal processor is designed with a combination of fixed and adaptive equalization means, along with low-speed signal generation and coefficient calculation mechanisms, allowing for high-performance equalization of various distortions by using fixed equalization coefficients for known distortions and adaptive methods for dynamic distortions, while optimizing circuit efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a TDE circuit with adequate compensation performance is implemented, then signal quality is improved, but circuit size becomes huge

Engineering Contradiction:
Improvesignal qualityVSAvoidcircuit size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The equalization function is divided into two segments: FDE circuit for high-performance fixed equalization of known static distortion, and TDE circuit for adaptive equalization of dynamic distortion. This segmentation allows each circuit to be optimized for its specific function, reducing the overall circuit size while maintaining signal quality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic control of the TDE circuit by adaptively adjusting filter coefficients based on polarization variations. This allows the TDE circuit to maintain adequate performance only when needed, reducing computational load and circuit complexity compared to a fully high-performance TDE circuit.

Inventive Principle:
Principle #15Dynamics

2Productivity

If oversampling rate for TDE circuit is reduced, then circuit efficiency is improved, but equalization performance deteriorates

Engineering Contradiction:
Improvecircuit efficiencyVSAvoidequalization performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies different oversampling rates to different circuits based on their specific requirements. The FDE circuit uses a higher oversampling rate appropriate for its fixed equalization function, while the TDE circuit uses a reduced oversampling rate suitable for adaptive equalization, optimizing overall system efficiency.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the oversampling rate parameter for the TDE circuit to a value lower than that of the FDE circuit. This parameter adjustment improves circuit efficiency while the adaptive coefficient control compensates for the reduced sampling rate, maintaining adequate equalization performance.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If computation precision for TDE circuit is reduced, then circuit efficiency is improved, but equalization performance deteriorates

Engineering Contradiction:
Improvecircuit efficiencyVSAvoidequalization performance
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent reduces the computation precision parameter for the TDE circuit compared to the FDE circuit. This reduction improves circuit efficiency by reducing the computational complexity of coefficient calculations, while the adaptive nature of the TDE circuit maintains adequate equalization performance for dynamic distortion compensation.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10171177B2Digital signal processor, digital optical receiver using the same, and digital signal processing method
Publication Date: 2019.01.01 NEC CORP
  • US10171177B2 patent drawing
  • US10171177B2 patent drawing
  • US10171177B2 patent drawing

AI summary

It is difficult to obtain a demodulated signal with high signal quality in a digital optical receiver because it is difficult to compensate for each of different types of waveform distortion by a high-performance equalization process; therefore, a digital signal processor according to an exemplary aspect of the present invention includes a fixed equalization means for performing a distortion compensation process based on a fixed equalization coefficient on an input digital signal; an adaptive equalization means for performing an adaptive distortion compensation process based on an adaptive equalization coefficient on an equalized digital signal output by the fixed equalization means; a low-speed signal generation means for generating a low-speed digital signal by intermittently extracting one of the input digital signal and the equalized digital signal; a low-speed equalization coefficient calculation means for calculating a low-speed equalization coefficient to be used for a distortion compensation process of the low-speed digital signal; and a fixed equalization coefficient calculation means for calculating the fixed equalization coefficient by using at least a predetermined coefficient out of the low-speed equalization coefficient and the predetermined coefficient.