DSP Pattern Detection Circuit for ALU Termination Conditions
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Solution Overview
Problem
The increasing demand for real-time, concurrent arithmetic operations in digital signal processing applications, such as in 3G base stations, is not adequately met by traditional DSP chips or Programmable Logic Devices (PLDs) due to bottlenecks in the PLD fabric, necessitating a more efficient digital signal processing solution.
Innovation Solution
An integrated circuit (IC) with a digital signal processing unit, pattern detector circuit, and cascaded DSP elements that include arithmetic logic units (ALUs) and multiplexers for enhanced arithmetic and logical operations, along with a comparison circuit and masking mechanisms to improve processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple DSP elements are configured in the programmable logic of a PLD to allow concurrent DSP operations, then the quantity of arithmetic operations per second is improved, but the PLD fabric becomes a bottleneck that limits further performance improvement
Solution Approach 1:
The patent divides the DSP processing function into separate, dedicated elements (DSP elements with ALUs, multipliers, and accumulators) that are cascaded together. Each element is a self-contained unit that performs specific arithmetic operations, allowing concurrent processing without the interconnect complexity of a full PLD fabric. This segmentation resolves the contradiction by achieving high arithmetic throughput through specialized modules rather than general-purpose programmable logic.
2Productivity
If more DSP microprocessors are added to run in parallel to meet increasing demand for arithmetic operations, then the productivity is improved, but the device complexity and interconnect requirements increase
Solution Approach 1:
The patent merges multiple DSP functional units (multipliers, accumulators, ALUs, and registers) into integrated cascaded elements. Instead of using separate microprocessors with extensive interconnects, the invention combines arithmetic functions within unified DSP elements that can be chained together with minimal interconnection, reducing overall system complexity while maintaining high parallel processing capability.
3Productivity
If application specific circuits are used to replace multiple DSP elements in PLD, then the PLD fabric bottleneck is reduced, but the adaptability and reconfigurability decrease
Solution Approach 1:
The patent implements dynamic reconfigurability within the cascaded DSP element structure. The elements can be programmatically configured to perform different arithmetic operations and can be dynamically allocated or reconfigured based on processing requirements. This dynamic capability allows the system to adapt to different DSP algorithms while maintaining the high performance of application-specific circuits, resolving the contradiction between performance and adaptability.
Data Source
AI summary
A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.