Triple-Slice DSP Register Voting for Radiation Upset Tolerance
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Solution Overview
Problem
Electronic systems operating in harsh radiation environments face single-event upsets due to high-energy particles, which can corrupt digital information, necessitating improved fault tolerance and reliability in processor operations.
Innovation Solution
A system with triple modular redundancy using three interconnected digital signal processors that perform bitwise majority vote (RMAJ) and sum of two closest (RSOC) operations to correct single-event upsets and ensure identical digital values across processors, ensuring reliable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triple modular redundancy is employed to improve reliability in radiation environments, then fault tolerance is improved, but device complexity increases
Solution Approach 1:
The patent merges the three replicated processors into a single integrated circuit chip, combining multiple functions (processing, voting, correction) into one unified device. This reduces the overall system complexity compared to using three separate physical processors with external voting logic, while maintaining the triple modular redundancy architecture for fault tolerance.
Solution Approach 2:
Each processor slice is designed with multi-functionality, capable of performing both normal processing operations and participation in majority voting operations. The slices can dynamically switch between executing their primary function and participating in fault detection and correction, reducing the need for dedicated separate voting circuitry and thereby reducing overall device complexity.
2Reliability
If majority voting systems are used to resolve single-event upsets, then reliability is improved, but processing speed decreases
Solution Approach 1:
The system performs preliminary comparison of the three processor outputs continuously or at critical decision points, so that when a single-event upset is detected, the majority voting correction can be applied immediately without waiting for external detection and intervention. This preliminary action minimizes the speed penalty by having the voting logic ready and integrated within the processor slices themselves.
3Measurement precision
If replicated signal paths are used to detect single-event upsets, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The detection, comparison, and correction functions are merged into the integrated circuit structure of the processor slices themselves, rather than using separate external circuits. The replicated signal paths are implemented as parallel data buses within the chip, reducing the complexity of external wiring and interconnections while maintaining the ability to detect and correct single-event upsets with high precision.
Data Source
AI summary
A system includes a control loop signal path. The signal path includes three processors. Each processor (“slice”) includes an ADC, a digital signal processor (DSP), and a DAC. The DSPs execute identical programs of instructions, so that at any given time they are executing the same instruction. The DSP of the slice executes an instruction that performs a “register sum of two closest” (RSOC) operation. The instruction identifies a register of the slice, and the data content of this register is output to the other slices. The DSP performs a “sum of two closest” operation on: 1) the data content of the register, 2) the data content to the corresponding registers in the other slices. The DSP determines which two of these values are numerically the closest, generates a result value that is a function of these two values (for example, the sum), and writes the result into the register.