DSP SAD Unit for Dynamic Block Search and Motion Estimation
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Solution Overview
Problem
The computation of sum of absolute differences (SAD) between pixel blocks for determining motion vectors in video compression is computationally intensive, particularly due to the need for full search block matching using single horizontal pixel line searches for specific macro block sizes.
Innovation Solution
A digital signal processor that performs plural sums of absolute values in a single operation using two sets of rows with absolute value difference units and row summers, allowing for offset candidate pixels relative to reference pixels and employing mask inputs to configure different block sizes and search methods, including dual horizontal pixel line searches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If single horizontal pixel line search is used for full search block matching, then motion vector determination can be performed, but computational intensity and power consumption are excessively high
Solution Approach 1:
The pixel data is divided into multiple lanes (e.g., 4 lanes of 16 pixels each) that can be processed simultaneously. Each lane processes a subset of pixels in parallel, breaking down the single-line search into multiple concurrent operations that reduce overall computational burden per operation while maintaining full search capability.
Solution Approach 2:
Multiple pixel lines are merged into a single wide operation by processing multiple horizontal pixel lines simultaneously using packed pixel data structures. This combines what would traditionally be separate sequential operations into one parallel operation, improving computational efficiency and reducing power consumption per unit of work.
2Productivity
If SAD operations are performed sequentially for different block sizes, then accurate motion estimation is achieved, but processing time increases
Solution Approach 1:
The processor dynamically configures the block size and search area using control registers that can be programmed for different macro block sizes (16×16, 8×8, 4×4) and search ranges. This dynamic reconfiguration allows the same hardware to efficiently handle multiple block sizes without sequential processing, as the parallel architecture adapts to the required configuration.
Solution Approach 2:
A single SAD computation unit is designed to handle multiple block sizes and search configurations through programmable control registers. Instead of having separate dedicated units for each block size, one universal unit can be configured via control registers to perform SAD calculations for 16×16, 8×8, 4×4 blocks and various search areas, reducing processing time through parallel execution capability.
Data Source
AI summary
This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.