DSP SERDES Filter Architecture for Long-Reach ISI and Reflection Cancellation
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Solution Overview
Problem
High-speed digital signal processing (DSP)-based serializer-deserializers (SERDES) face challenges in maintaining high efficiency and reducing power usage and chip area, especially in long-reach transmission channels where inter-symbol interference (ISI) is significant, and reflection cancellation and fast-timing recovery are required.
Innovation Solution
The proposed solution involves a low-power, low-area architecture for high-performance DSP-based SERDES that incorporates a cascaded combination of three filters and an optional interpolator. This architecture includes a short receive FFE filter for low-latency timing recovery, a reflection canceller FIR filter to cancel reflections, and a noise-shaping partial-response FIR filter to address ISI, while minimizing active taps and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a long feed-forward equalizer (FFE) with many taps is used to equalize reflections in long-reach channels, then the equalization performance is improved, but the power consumption and chip area increase
Solution Approach 1:
The patent divides the equalization function into two separate modules: a feed-forward equalizer (FFE) for reducing inter-symbol interference and a decision-feedback equalizer (DFE) for canceling reflections. This segmentation allows each module to be optimized independently, with the DFE using fewer taps than a conventional long FFE would require, thereby reducing power consumption while maintaining equalization performance.
Solution Approach 2:
The patent introduces an intermediary decision-feedback mechanism that uses previous decisions about transmitted symbols to cancel reflections. This DFE acts as a mediator between the received signal and the final decision, enabling effective reflection cancellation without requiring a proportionally large increase in FFE taps, thus controlling power consumption.
2Reliability
If a long feed-forward equalizer (FFE) with many taps is used to equalize reflections in long-reach channels, then the equalization performance is improved, but the chip area increases
Solution Approach 1:
The patent divides the equalization function into two separate modules: a feed-forward equalizer (FFE) for reducing inter-symbol interference and a decision-feedback equalizer (DFE) for canceling reflections. This segmentation allows each module to be optimized independently, with the DFE using fewer taps than a conventional long FFE would require, thereby reducing chip area while maintaining equalization performance.
3Speed
If a separate shorter FFE is dedicated to the timing recovery path to achieve fast timing recovery, then the timing recovery speed is improved, but the device complexity and redundancy increase
Solution Approach 1:
The patent implements a dynamic timing recovery mechanism that operates on the FFE output signal with a limited number of taps. The timing recovery loop dynamically adjusts its parameters based on the received signal characteristics, enabling fast convergence without requiring a separate dedicated FFE path. This dynamic approach achieves fast timing recovery while avoiding the redundancy and complexity of having multiple FFE structures.
Data Source
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AI summary
A digital signal processing, DSP, -based serializer-deserializer, SERDES, includes a first filter (624) configured to mitigate inter-symbol interference, ISI),attributed to dispersion associated with a long-reach transmission medium. The SERDES includes a second filter (432, 632) configured to shape the ISI. The SERDES includes also includes a third filter (636) coupled in parallel with the second filter (432, 632) and configured to reduce ISI attributed to reflections associated to both near-zero delays and long delays.