DSP SERDES Filter Architecture for Long-Reach ISI and Reflection Cancellation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DSP-based SERDES face challenges in maintaining high efficiency and reducing power and area while effectively handling long-reach transmission channels with significant inter-symbol interference (ISI) and reflection, leading to increased complexity and latency.
Innovation Solution
Implementing a low-power, low-area architecture with a cascaded combination of three filters - a short RX-FFE, a reflection canceller FIR, and a noise-shaping PR FIR filter - along with an optional interpolator to achieve fast-timing recovery and reflection cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a long FFE with many taps is used to equalize reflections in long-reach channels, then the equalization performance is improved, but the power consumption and chip area increase
Solution Approach 1:
The patent divides the equalization function into two separate modules: a long FFE for equalizing reflections at long delays, and a short FFE for equalizing near-zero delay ISI and providing timing recovery. This segmentation allows each module to be optimized independently, reducing the total power consumption compared to using a single long FFE for all functions.
Solution Approach 2:
The patent uses a short FFE with fewer taps than a conventional long FFE would require, combined with a decision-feedback equalizer (DFE) to handle the remaining ISI. This partial action approach achieves sufficient equalization performance while significantly reducing the number of taps and associated power consumption in the FFE section.
2Reliability
If a long FFE with many taps is used to equalize reflections in long-reach channels, then the equalization performance is improved, but the chip area increases
Solution Approach 1:
The patent segments the equalization function into a long FFE for long-delay reflections and a short FFE for near-zero delay ISI, reducing the total number of taps required in the FFE section and thereby reducing chip area.
Solution Approach 2:
The patent introduces a decision-feedback equalizer (DFE) as an intermediary component that handles the ISI equalization function, allowing the FFE to be shortened. The DFE uses past decisions to cancel ISI, reducing the burden on the FFE and reducing the number of taps needed.
3Reliability
If a long FFE is used to equalize reflections, then the equalization capability is improved, but the latency increases causing loss of timing margin
Solution Approach 1:
The patent segments the equalization function by delay range, assigning long-delay reflection equalization to the long FFE and near-zero delay ISI equalization to the short FFE. This allows the timing recovery path to use the short FFE with lower latency, preserving timing margin while maintaining equalization capability for long-delay reflections through the separate long FFE path.
4Speed
If a separate short FFE is dedicated to the timing recovery path, then the timing recovery speed is improved, but the device complexity and redundancy increase
Solution Approach 1:
The patent segments the FFE into long and short versions with distinct functions: the long FFE handles reflections, while the short FFE handles near-zero delay ISI and provides timing recovery. This functional segmentation eliminates the need for a separate dedicated short FFE in the timing recovery path, reducing redundancy and complexity while maintaining fast timing recovery capability.
Data Source
AI summary
A digital signal processing (DSP)-based serializer-deserializer (SERDES) includes a first filter configured to mitigate inter-symbol interference (ISI) attributed to dispersion associated with a long-reach transmission medium. The SERDES includes a second filter configured to shape the ISI. The SERDES includes also includes a third filter coupled in parallel with the second filter and configured to reduce ISI attributed to reflections associated to both near-zero delays and long delays.