Shared Interrupt Control for DSP Thread Latency
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Solution Overview
Problem
Existing digital signal processors (DSPs) face complexities in hardware design and programming due to per-processor and per-thread interrupt handling, leading to inefficient interrupt processing and increased latency in multi-threaded environments.
Innovation Solution
A shared interrupt control method and system for DSPs that associates multiple processing threads with an interrupt register, allowing each thread to receive only specific interrupts based on predetermined masks, enabling efficient and flexible interrupt processing without the need for per-processor or per-thread handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If per-processor or per-thread interrupt handling is implemented, then interrupt processing capability is provided, but hardware design complexity and programming complexity increase
Solution Approach 1:
The patent merges interrupt handling into a shared resource that is common to all threads rather than providing separate per-thread interrupt controllers. The interrupt controller shares interrupt handling resources across multiple threads, eliminating the need for duplicate hardware components and reducing overall system complexity while maintaining the ability to handle interrupts efficiently for each thread.
Solution Approach 2:
The shared interrupt controller is designed to serve multiple threads universally, with each thread capable of receiving interrupts through a common interface. The controller can dynamically allocate interrupt handling to any available thread, making the system more flexible and reducing hardware requirements compared to dedicated per-thread controllers.
2Adaptability or versatility
If per-processor or per-thread interrupt handling is implemented, then interrupt processing capability is provided, but programming complexity increases
Solution Approach 1:
The patent simplifies programming by merging interrupt handling into a unified model where threads share common interrupt registration and handling mechanisms. Developers need to implement interrupt handlers only once and can serve multiple threads through a shared controller, reducing code duplication and simplifying the programming model compared to per-thread implementations.
3Device complexity
If shared interrupt control is implemented, then hardware complexity is reduced, but interrupt processing efficiency may be compromised
Solution Approach 1:
The shared interrupt controller dynamically selects which thread should handle a given interrupt based on current system state, thread availability, and interrupt priority. This dynamic thread selection mechanism ensures that interrupts are processed efficiently by assigning them to the most appropriate available thread, maintaining high processing efficiency despite the shared hardware architecture.
Data Source
AI summary
Techniques for the design and use of a digital signal processor, including (but not limited to) processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system process interrupts arising in a multithreaded processor by receiving in an interrupt register a plurality of interrupts of a statistically indeterminate interrupt type and then associating a plurality of processing threads with the interrupt register for receiving the interrupt from the interrupt register. The method and system mask at least a subset of the plurality of processing threads so as to receive within each of the threads within the subset only ones of the plurality of interrupts of one or more predetermined types, thereby controlling on a per thread basis the processing of the plurality of interrupts according to the mask associated with a particular thread.