DSP Slice Targeting Engine for FPGA Code Mapping
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Solution Overview
Problem
The performance of Field Programmable Gate Arrays (FPGAs) is limited by clock speed, and existing methods for configuring DSP operations often fail to efficiently map model elements to specialized DSP slices, leading to suboptimal performance due to architectural differences across various FPGA manufacturers and models.
Innovation Solution
A system and method for automatically generating code that maps model elements to DSP slices of a target FPGA device by using a DSP slice targeting engine, which accesses a hardware characterization database to determine optimal mapping, adding pipeline registers as needed to achieve deterministic mapping and balance delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing methods for configuring DSP operations are used, then general compatibility is maintained, but mapping efficiency to DSP slices is poor leading to suboptimal performance
Solution Approach 1:
The system changes parameters by using a hardware characterization database that stores specific architectural parameters for different FPGA devices. The DSP slice targeting engine queries this database to obtain device-specific parameters and uses them to generate optimized mapping configurations, transforming the mapping process from generic to parameter-specific optimization.
Solution Approach 2:
The hardware characterization database is pre-populated with architectural information for various FPGA devices before the mapping process begins. This preliminary preparation allows the DSP slice targeting engine to quickly retrieve and apply optimized mapping strategies without performing complex analysis during the actual code generation phase.
2Ease of operation
If model elements are mapped to DSP slices without considering architectural differences, then ease of configuration is maintained, but performance is limited by clock speed
Solution Approach 1:
The DSP slice targeting engine acts as an intermediary between the high-level model elements and the target FPGA architecture. It translates model elements into DSP slice-specific configurations by querying the hardware characterization database, thereby bridging the gap between generic modeling and architecture-specific optimization without requiring users to manually handle architectural details.
Solution Approach 2:
The system segments the configuration process into distinct components: the hardware characterization database stores architectural information, the DSP slice targeting engine performs mapping optimization, and the code generator produces optimized code. This segmentation allows each component to specialize in one aspect, maintaining ease of use while achieving performance optimization.
3Manufacturing precision
If pipeline registers are added to achieve deterministic mapping, then mapping precision is improved, but device complexity increases
Solution Approach 1:
The system dynamically determines the number and placement of pipeline registers based on the specific target device architecture queried from the hardware characterization database. Rather than using a fixed pipeline structure, the DSP slice targeting engine adapts the pipeline configuration to match the target device's capabilities, achieving deterministic mapping with minimal necessary complexity.
Data Source
AI summary
Systems and methods automatically generate code from an executable model. The code may be generated from one or more in-memory representations constructed for the model. The in-memory representations may be analyzed, and portions that can be mapped to DSP slices of a programmable logic device may be identified. The portions may be modified based on information for a particular programmable logic device, such as the structure of the device's DSP slices. The modifications may ensure that elements of the generated code get mapped to DSP slices, when the generated code is used to synthesize the programmable logic device.