Iterative DSP Timing Error Detection With Computation Skipping
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Solution Overview
Problem
Existing digital signal processing systems face challenges in maintaining constant throughput and avoiding throughput penalties due to timing errors, especially when operating beyond critical voltage or frequency limits, leading to unacceptable output quality and increased power consumption.
Innovation Solution
A signal processing device employing a computation-skip scheme that detects timing errors and adjusts the number of computation iterations based on detected timing violations, allowing the system to operate correctly even at sub-critical conditions by skipping iterations to ensure sufficient time for subsequent computations, thereby reducing power consumption and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the system operates beyond critical voltage or frequency limits to improve speed and reduce power consumption, then power efficiency improves, but timing errors increase leading to unacceptable output quality
Solution Approach 1:
The system dynamically adjusts the number of computation iterations based on detected timing violations. When timing errors are detected during operation beyond critical limits, the system adaptively reduces iterations to maintain reliability while preserving the benefits of operating at higher voltage/frequency for power efficiency.
Solution Approach 2:
A timing error detection mechanism provides real-time feedback about timing violations. This feedback loop allows the system to monitor operating conditions and adjust computation iterations accordingly, enabling reliable operation beyond critical voltage or frequency limits by compensating for timing errors through iterative adjustment.
2Reliability
If conventional error correction schemes are used to correct timing errors, then output quality is maintained, but throughput decreases due to extra computation cycles
Solution Approach 1:
Instead of performing full error correction that guarantees output quality, the system performs partial correction by reducing computation iterations to an acceptable level. This partial action maintains sufficient output quality while avoiding the throughput penalty of complete error correction, accepting some degradation in exchange for maintained productivity.
Data Source
AI summary
The present disclosure relates to an error resilient scheme for a signal processing device configured to perform iterative processing on clocked input data and to provide output data. The signal processing device includes a computation circuit comprising at least one computation unit circuit configured to perform one computation in each iteration on the clocked input data and to provide or generate processed data, and a selection circuit configured to provide as the output signal either the processed data or the clocked input data, depending on a control signal representative of a set-up timing error detected in an input data.