DSP Video Port Interface Packetization for Ethernet Switching

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Solution Overview

Problem

Current digital signal processors (DSPs) face challenges in interconnecting multiple processors for real-time video processing due to insufficient bandwidth and asynchronous interfaces, which are not suitable for high-definition video frame rates, and shared memory approaches are limited by signal integrity issues.

Innovation Solution

The system utilizes the high-bandwidth, synchronous video port interface (VPIF) of DSPs to packetize video frames into VLAN-tagged Ethernet packets, enabling transmission over a 10 or 20 Gb/s Ethernet switching fabric, allowing for scalable media processing by synchronizing and routing video data across multiple DSPs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple DSPs are interconnected for real-time video processing, then processing capability and scalability are improved, but bandwidth insufficiency and interface asynchrony worsen

Engineering Contradiction:
Improvevideo processing capabilityVSAvoidinterface bandwidth
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The video frame is segmented into multiple packets for transmission over the Ethernet network. Each packet contains a portion of the video frame data along with control information, allowing the high-bandwidth video data to be distributed across multiple network packets, thereby resolving the bandwidth limitation of individual interfaces while maintaining overall high throughput

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The video port interface is designed to serve multiple functions: it handles both the high-bandwidth video data transmission and the control signaling simultaneously. The interface can operate in different modes (packetized video mode, control mode) and supports multiple video formats and resolutions, making it a universal interface that addresses both bandwidth and flexibility requirements

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If shared memory approach is used for DSP interconnection, then simplicity of implementation is improved, but signal integrity deteriorates

Engineering Contradiction:
Improveinterconnection complexityVSAvoidsignal integrity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

An Ethernet network acts as an intermediary between DSPs, replacing direct shared memory connections. This intermediary provides electrical isolation and impedance matching, preventing signal integrity issues while maintaining simple implementation through standard Ethernet protocols and switching fabric

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If video frames are packetized over Ethernet network, then scalability and flexibility are improved, but transmission latency increases

Engineering Contradiction:
Improveresource allocation flexibilityVSAvoidtransmission latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

Video frames are packetized at the source DSP before transmission, with all necessary control information and ordering data embedded in advance. This preliminary packetization allows the receiving DSP to reconstruct frames immediately upon receipt without waiting for additional control signals, minimizing processing latency while maintaining scalability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The packetized video transmission maintains continuous data flow across the Ethernet network by overlapping packet transmission with reception. Multiple packets are transmitted and received in parallel through the switching fabric, ensuring continuous useful action without idle waiting periods, thereby reducing overall latency

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS8355398B2Transporting real time video frames over an Ethernet network
Publication Date: 2013.01.15 CISCO TECHNOLOGY INC
  • US8355398B2 patent drawing
  • US8355398B2 patent drawing
  • US8355398B2 patent drawing

AI summary

Systems and methods for real time data processing using a switching network and multiple digital signal processors (DSPs). In an embodiment, the system includes a first digital signal processor having a video port interface, a first interface disposed between the video port interface of the first digital signal processor and a switching network, a second digital signal processor having a video port interface, and a second interface disposed between the video port interface of the second digital processor and the switching network. The first interface is configured to parse a VSYNC line of a video frame that is output from the first digital signal processor via its video port interface to generate a multiplexing table based upon which scan lines of the video frame are broken up into packets compatible with the switching network such that the packets can be transmitted over the switching network and be received by the second interface and the second digital signal processor via its video port interface.