DSPUs in Packet Pipelines for Reconfigurable Line-Rate Processing
Solution Overview
Problem
Current data-plane algorithms in network switches require dedicated hardware for line-rate processing, making them rigid and inflexible, preventing reconfigurability and limiting the ability to implement new algorithms without rebuilding hardware.
Innovation Solution
A synchronous packet-processing pipeline populated with data-plane stateful processing units (DSPUs) that maintain and update their own state information, allowing for programmable and flexible processing of packets with fixed latency, enabling the implementation of new data-plane algorithms without hardware changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated hardware is used for data-plane algorithms, then line-rate processing is achieved, but reconfigurability is lost
Solution Approach 1:
The patent applies dynamics by transitioning from static dedicated hardware to dynamic programmable processors (DSPUs) that can be reconfigured at runtime. Each DSPU maintains state information and can be programmed to implement different data-plane algorithms, enabling the system to adapt to changing requirements while maintaining line-rate processing capability through hardware-accelerated execution.
Solution Approach 2:
The patent implements universality by designing DSPUs as multi-functional processing units that can execute various data-plane algorithms through programming. Instead of requiring separate dedicated hardware for each algorithm, a single DSPU can be reprogrammed to implement different algorithms (e.g., congestion control, load balancing, packet inspection), making the system universally applicable to multiple functions.
2Adaptability or versatility
If hardware is rebuilt to implement new algorithms, then new data-plane algorithms can be executed, but system complexity and deployment time increase
Solution Approach 1:
The patent applies copying by using programmable processors that replicate the functionality of dedicated hardware through software instructions. Instead of physically rebuilding hardware, the system copies the algorithmic logic into the DSPU's instruction memory, allowing new algorithms to be deployed by loading new instruction sets rather than manufacturing new hardware circuits.
Solution Approach 2:
The patent substitutes the mechanical process of hardware rebuilding with a software-based approach. New data-plane algorithms are implemented by programming DSPUs with new instruction sets, replacing the need for physical hardware modification, circuit board assembly, and device fabrication with simple software loading and configuration.
3Adaptability or versatility
If programmable processors are used, then reconfigurability is achieved, but processing speed may decrease
Solution Approach 1:
The patent applies segmentation by dividing the packet processing function into multiple independent DSPUs operating in parallel within the data-plane pipeline. Each DSPU handles specific processing tasks with fixed-latency operations, and multiple DSPUs work simultaneously on different packets or processing stages, achieving both programmability and high throughput by distributing the workload across segmented processing units.
Data Source
AI summary
A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.