Multi-layer DSRD Stack with Epitaxial Tunneling Interface

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Solution Overview

Problem

Conventional methods for fabricating multi-layer Drift Step Recovery Diodes (DSRDs) face challenges due to the introduction of intermediate metallic layers, which result in higher contact resistance and voids at the interfaces between diodes, leading to suboptimal performance and increased fabrication costs.

Innovation Solution

The approach involves growing the entire stack of DSRDs epitaxially on a substrate without intermediate metallic layers, using a method that includes alternating layers of dopants to form a tunneling diode at the interface, which demonstrates a linear current-voltage characteristic, thereby eliminating the need for metallic layers and reducing fabrication time and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If intermediate metallic layers are used in conventional multi-layer DSRD fabrication, then diodes can be stacked together, but contact resistance increases and voids form at interfaces

Engineering Contradiction:
Improveinterface qualityVSAvoidcontact resistance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent removes intermediate metallic layers from the multi-layer DSRD structure, eliminating the source of contact resistance and void formation. The diodes are stacked directly with semiconductor-to-semiconductor contact, extracting the harmful metallic intermediary that caused interface defects.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs asymmetric doping at the interface between stacked diodes, creating a tunneling diode with highly doped regions on one side and lightly doped regions on the other. This asymmetric doping profile enables low-resistance contact without requiring metallic layers, resolving the contradiction between interface quality and contact resistance.

Inventive Principle:
Principle #4Asymmetry

2Ease of manufacture

If intermediate metallic layers are used for stacking DSRDs, then diodes can be connected, but fabrication complexity and cost increase

Engineering Contradiction:
Improvefabrication processVSAvoidstructure complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent merges the stacking process with the epitaxial growth process, forming multiple DSRDs in a single continuous growth step. This eliminates separate metallization and bonding steps, combining what were previously distinct fabrication operations into one integrated process, thereby reducing both fabrication complexity and device structure complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the doping parameters during epitaxial growth to create the desired multi-layer structure with tunneling diodes at interfaces. By controlling dopant concentration and distribution during growth, the patent achieves complex functionality without complex fabrication steps, simplifying the manufacturing process while maintaining device performance.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If conventional fabrication methods are used with metallic layers, then diodes can be formed, but layer thickness control is poor

Engineering Contradiction:
Improvelayer thickness controlVSAvoidfabrication time
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent utilizes epitaxial growth parameters (temperature, pressure, gas flow, dopant concentration) to precisely control layer thickness and doping profiles. This parameter control during growth enables accurate thickness specification without requiring additional processing steps, achieving high manufacturing precision while maintaining efficient fabrication.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method simplifies the fabrication process, reduces voids and contact resistance, and enhances the performance of multi-layer DSRDs by allowing better control over layer thickness and achieving superior electrical characteristics, such as lower reverse breakdown voltage and higher turn-on voltage.

Implementation Method 1

The first layer of the second DSRD and the third layer of the first DSRD are degenerate to form a tunneling diode at an interface of the first DSRD and second DSRD, the tunneling diode demonstrating a linear current-voltage characteristic

Methodology Applied
Scientific EffectTunneling: Franz-Keldysh Effect

Implementation Method 2

growing, for each DSRD, a first layer having a first type of dopant, a second layer forming a region with at least ten times lower concentration of dopants compared to adjacent layers thereto, and a third layer having a second type of dopant

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS11322626B2Tunnel drift step recovery diode
Publication Date: 2022.05.03 BAE SYSTEMS LAND & ARMAMENTS LP
  • US11322626B2 patent drawing
  • US11322626B2 patent drawing
  • US11322626B2 patent drawing

AI summary

Devices, methods and techniques are disclosed for providing a multi-layer diode without voids between layers. In one example aspect, a multi-stack diode includes at least two Drift Step Recovery Diodes (DSRDs). Each DSRD comprises a first layer having a first type of dopant, a second layer forming a region with at least ten times lower concentration of dopants compared to the adjacent layers, and a third layer having a second type of dopant that is opposite to the first type of dopant. The first layer of a second DSRD is positioned on top of the third layer of first DSRD. The first layer of the second DSRD and the third layer of the first DSRD are degenerate to form a tunneling diode at an interface of the first DSRD and second DSRD, the tunneling diode demonstrating a linear current-voltage characteristic.