DTC-Assisted ADPLL Error Compensation for Low Phase Noise
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Solution Overview
Problem
Conventional digital-to-time converter (DTC)-assisted all digital phase locked loop (ADPLL) circuits face challenges due to non-linearity caused by mismatch between delay cells and routing paths, leading to degraded spurious and in-band noise performance, which requires complex calibration techniques increasing IC implementation area, power consumption, and settling time.
Innovation Solution
A DTC error compensator is introduced, comprising a de-multiplexer, multiplexer, and low pass filter circuits configured based on the reference clock signal, and integrators based on a frame clock signal, to filter and rectify phase offset signals, reducing DTC error and improving noise performance by subtracting the error from the phase offset signal, thereby enhancing the ADPLL's noise and spurious tone levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex background non-linearity calibration technique is employed to mitigate DTC non-linear errors, then noise and spurious performance is improved, but IC implementation area, power consumption, and settling time increase
Solution Approach 1:
The patent applies preliminary action by performing DTC error calibration frame-to-frame using low pass filter circuits that process phase offset signals before they are used in the ADPLL operation. The calibration is done in advance for each frame, storing corrected values in lookup tables that are then used during normal operation, eliminating the need for complex continuous calibration techniques.
Solution Approach 2:
The patent segments the calibration process into frame-based discrete units, where each frame undergoes independent DTC error calibration. The phase offset signal is divided into multiple components that are processed separately through different low pass filter circuits, and the calibration is performed on segmented portions of the signal rather than as a monolithic complex process.
2Reliability
If frame-to-frame DTC error calibration is performed using low pass filter circuits, then in-band phase noise and spurious tone levels are reduced, but power consumption and IC area increase
Solution Approach 1:
The patent applies partial action by using only the necessary portion of the phase offset signal for calibration purposes. The low pass filter circuits process only the relevant frequency components that contain DTC error information, filtering out unnecessary high-frequency components. This partial processing reduces the computational burden and power consumption compared to processing the entire signal spectrum.
3Device complexity
If DTC non-linearity is not compensated, then device complexity is reduced, but spurious and in-band noise performance degrades
Solution Approach 1:
The patent introduces an intermediary calibration mechanism using low pass filter circuits and lookup tables that mediate between the DTC non-linearity and the ADPLL performance. Instead of directly compensating for non-linearity through complex circuitry, the system uses the lookup tables as intermediaries that store pre-calibrated correction values, simplifying the hardware while maintaining performance.
Data Source
AI summary
A digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit is disclosed, which comprises: a DTC error compensator arranged to receive a phase offset signal being a processed output from a time-to-digital converter (TDC) circuit, the phase offset signal includes a DTC error corresponding to a phase difference between a reference clock signal processed by a DTC circuit and a feedback clock signal derived from an output signal of the ADPLL circuit. The compensator is arranged to process the phase offset signal for generating a digital signal representative of the DTC error, which is provided as an output signal. Also, the output signal is arranged to be subtracted from the phase offset signal to obtain a phase rectified signal of the phase offset signal.