DTC Biasing Scheme for Temperature-Stable Full-Scale Delay
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Solution Overview
Problem
Switched capacitor and resistor-capacitor Digital-To-Time Converters (DTCs) suffer from temperature dependency issues, leading to increased full-scale delay ranges that can cause phase locked loop (PLL) circuits to malfunction due to noise and performance degradation.
Innovation Solution
A biasing scheme using a complementary-to-absolute-temperature (CTAT) reference signal and a low dropout regulator (LDO) circuit to stabilize the DTC full-scale delay range by compensating for temperature variations, combined with a programmable capacitor array and control circuit for precise delay adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If switched capacitor DTC is used, then the DTC can be implemented with standard components, but the DTC becomes noisy and does not compensate for temperature dependency
Solution Approach 1:
The patent changes the operating parameters of the DTC by introducing a temperature-dependent bias voltage that adjusts the delay characteristics. The bias voltage is generated to have a negative temperature coefficient that compensates for the positive temperature coefficient of the delay elements, thereby stabilizing the full-scale delay range across temperature variations.
Solution Approach 2:
The patent implements a feedback mechanism where the temperature dependency of the delay elements is sensed and compensated by adjusting the bias voltage. The system uses the temperature characteristics of the delay elements to generate a compensating bias signal that feeds back to the DTC, creating a closed-loop temperature compensation system.
2Reliability
If RC DTC is used, then transistor noise sensitivity is reduced, but resistance and capacitance values increase with temperature causing full-scale delay range to increase
Solution Approach 1:
The patent changes the voltage parameter applied to the RC delay elements. By introducing a bias voltage with a negative temperature coefficient, the patent compensates for the natural increase in RC time constant with temperature, thereby stabilizing the full-scale delay range while maintaining the noise immunity benefits of RC DTC.
3Device complexity
If temperature compensation is not implemented, then the DTC circuit is simple, but the full-scale delay range increases with temperature causing PLL to lose lock
Solution Approach 1:
The patent introduces a bias generation circuit as an intermediary component that mediates between the temperature variations and the DTC delay elements. This bias circuit generates a compensating voltage that offsets the temperature-induced delay changes, protecting the PLL from losing lock while adding minimal complexity to the overall system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Stabilizes the DTC full-scale delay range across temperature variations, reducing the change in delay from 35 ps to 8 ps and maintaining supply voltage stability, thus enhancing PLL circuit performance.
Implementation Method 1
A biasing scheme using a complementary-to-absolute-temperature (CTAT) reference signal and a low dropout regulator (LDO) circuit to stabilize the DTC full-scale delay range by compensating for temperature variations
Implementation Method 2
A biasing scheme using a complementary-to-absolute-temperature (CTAT) reference signal
Data Source
AI summary
A digital-to-time converter (DTC) is disclosed. In some embodiments, the DTC includes a bias circuit, a delay circuit, and a replica. The delay circuit is operably connected to the bias circuit. Furthermore, a replica circuit is operably connected to the bias circuit, wherein the bias circuit is operable to output a supply signal for the delay circuit and the replica circuit that has a negative slope with respect to a signal level of the supply signal and temperature.