DTC Biasing Scheme for Temperature-Stable PLL Delay Range

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Switched capacitor and resistor-capacitor Digital-To-Time Converters (DTCs) suffer from temperature dependency issues, leading to increased full-scale delay ranges that can cause phase locked loop (PLL) circuits to malfunction.

Innovation Solution

A biasing scheme using a complementary-to-absolute-temperature (CTAT) regulated reference signal and a programmable capacitor array to stabilize the DTC full-scale delay range, compensating for temperature variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If switched capacitor DTC or RC DTC is used, then the DTC can provide time-delayed output signal, but the full-scale delay range increases with temperature causing PLL circuit to lose lock

Engineering Contradiction:

ImprovePLL circuit lock stabilityVSAvoidtemperature dependency of delay range

Core Design Contradiction:

ReliabilityVSTemperature

Solution Approach 1:

The patent changes the parameter being controlled from capacitance values to resistance values. By using a programmable resistor array instead of a programmable capacitor array, the system exploits the negative temperature coefficient of resistance to counteract the positive temperature coefficient of capacitance, thereby stabilizing the full-scale delay range against temperature variations.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent converts the harmful effect of temperature-induced capacitance increase into a beneficial effect by using temperature-dependent resistance changes. The resistance values naturally decrease with temperature increase, which compensates for the capacitance increase, thus transforming the temperature dependency from a harmful factor into a self-compensating mechanism.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Object-generated harmful factors

If RC DTC is used instead of switched capacitor DTC, then transistor noise is reduced, but resistance and capacitance increase with temperature causing full-scale delay range to increase

Engineering Contradiction:

Improvetransistor noiseVSAvoidtemperature dependency of delay range

Core Design Contradiction:

Object-generated harmful factorsVSTemperature

Solution Approach 1:

The patent changes the dominant parameter from capacitance to resistance. By making the programmable element a resistor rather than a capacitor, the system maintains the low-noise advantage of RC DTC while adding temperature compensation through the resistance temperature relationship, thus resolving the temperature dependency issue without sacrificing noise performance.

Inventive Principle:

Principle #35Parameter changes

3Temperature

If full-scale delay range increases with temperature, then capacitance values increase, but this causes PLL circuit performance degradation and spur level increase

Engineering Contradiction:

Improvecapacitance value stabilityVSAvoidPLL circuit performance

Core Design Contradiction:

TemperatureVSReliability

Solution Approach 1:

The patent changes the controlled parameter from capacitance to resistance. Since resistance has a negative temperature coefficient while capacitance has a positive temperature coefficient, using resistance as the programmable parameter creates an automatic temperature compensation effect that stabilizes the full-scale delay range and prevents PLL performance degradation.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Stabilizes the DTC full-scale delay range, reducing temperature-induced variations and maintaining consistent performance in PLL circuits.

Implementation Method 1

Methodology Applied

Scientific EffectComplementary-to-absolute-temperature (CTAT) regulation:

Implementation Method 2

Capacitance values increase with temperature, which means an overall DTC full-scale delay range increases with temperature.

Methodology Applied

Scientific EffectCapacitance temperature compensation: Capacitance

Data Source

PatentUS12422783B2DTC biasing scheme for temperature compensation

Publication Date: 2025.09.23 QORVO US INC

AI summary

A digital-to-time converter (DTC) is disclosed. In some embodiments, the DTC includes a bias circuit, a delay circuit, and a replica. The delay circuit is operably connected to the bias circuit. Furthermore, a replica circuit is operably connected to the bias circuit, wherein the bias circuit is operable to output a supply signal for the delay circuit and the replica circuit that has a negative slope with respect to a signal level of the supply signal and temperature.