DTC Calibration for Fractional Clock Divider Gain and INL Errors
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Solution Overview
Problem
Existing clock division methods, such as integer frequency division, are limited in their ability to achieve high resolution in output clock signal frequencies due to an integer relationship between input and output clock signals, leading to issues like jitter and errors caused by gain and parametric integrated nonlinearity (INL) errors in fractional output dividers.
Innovation Solution
A circuit comprising a multi-modulus divider, delta-sigma modulator, digital-to-time converter (DTC), and calibration circuit that dynamically adjusts the DTC to correct for gain and INL errors, allowing for a fractional output divider that mitigates phase errors and maintains a periodic output clock signal without the constraints of integer frequency relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If integer frequency division is used, then the circuit structure is simple, but the output clock signal resolution is limited and jitter occurs
Solution Approach 1:
The patent employs a fractional output divider that dynamically varies its divide value in time, transitioning from static integer division to dynamic fractional division. This allows the output clock frequency to achieve high resolution without being constrained to integer relationships with the input clock, thereby resolving the contradiction between circuit simplicity and output resolution.
Solution Approach 2:
The patent changes the divide parameter from fixed integer values to dynamically varying fractional values. By using a delta-sigma modulator to generate a sequence of divide values whose average corresponds to the desired fractional divide ratio, the system achieves high-resolution output frequencies while managing the complexity through parameter optimization.
2Measurement precision
If fractional output divider with dynamic divide value is used, then output clock signal resolution is improved, but phase errors and jitter increase due to gain and INL errors
Solution Approach 1:
The patent introduces a calibration circuit that performs feedback correction for gain error and parametric integrated nonlinearity (INL) error in the digital-to-time converter (DTC). By measuring these errors and applying compensation, the system maintains high output resolution while significantly reducing phase errors and jitter, thus resolving the reliability issue.
Solution Approach 2:
The patent replaces the need for mechanical or physical stabilization methods with electronic calibration and correction. Instead of relying on physical clock signal stability, the system uses digital calibration circuits to electronically compensate for timing errors, substituting physical constraints with computational correction.
3Reliability
If calibration circuit is added to correct gain and INL errors, then phase errors and jitter are reduced, but device complexity increases
Solution Approach 1:
The patent performs calibration in advance during manufacturing or initialization, storing correction values in lookup tables (LUTs) or registers. This preliminary calibration action allows the system to operate with high precision during normal operation without requiring continuous complex calibration circuits, thereby reducing operational complexity while maintaining reliability.
Solution Approach 2:
The calibration circuit is designed to be integrated within the fractional output divider itself, allowing the system to self-calibrate without requiring external calibration equipment. The DTC and calibration circuit work together as a self-contained unit that automatically corrects its own errors, reducing the need for additional external components and simplifying the overall system architecture.
Data Source
AI summary
In some examples, a circuit includes a clock divider and a calibration circuit coupled to the clock divider. The clock divider includes digital-to-time converter (DTC). The calibration circuit configured to determine a gain error and a parametric integrated nonlinearity (INL) error of the DTC, determine a gain adjustment value and a INL adjustment value to compensate for the gain error and the INL error, and modify operation of the DTC according to the gain adjustment value and the INL adjustment value to correct for the gain error and the INL error.