DTC Calibration Circuit for Low-Jitter Frequency Division
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Solution Overview
Problem
Existing approaches for clock signal frequency division are limited in their ability to accurately adjust and stabilize the frequency and reduce jitter, particularly due to deviations in the transfer characteristic of digital-to-time converters (DTCs) caused by non-idealities such as gain errors, integrated non-linearity errors, and mismatch errors.
Innovation Solution
A system comprising a multi-modulus divider, delta-sigma modulator, and digital-to-time converter (DTC) with a calibration circuit, which includes a processing circuit to provide correction codes and adjust delay elements to mitigate errors, using auxiliary delay elements and a calibration circuit to dynamically correct for gain, INL, and mismatch errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional frequency division approaches are used, then the device complexity is reduced, but the measurement precision and manufacturing precision of the clock signal frequency and jitter are degraded
Solution Approach 1:
The frequency division system is segmented into multiple functional blocks: a multi-modulus divider for coarse frequency division, a digital-to-time converter (DTC) for fine delay adjustment, and a calibration circuit for error correction. Each block handles a specific aspect of frequency division, allowing high precision without requiring a single complex device.
Solution Approach 2:
The calibration circuit acts as an intermediary that measures the transfer characteristic deviations of the DTC and generates correction codes to compensate for gain errors, integrated non-linearity errors, and mismatch errors. This intermediary component enables high precision frequency division by actively correcting errors rather than relying on inherent device accuracy.
2Stability of the object's composition
If DTC transfer characteristic deviations are not corrected, then the device complexity is reduced, but the stability of the clock signal is degraded due to gain errors, integrated non-linearity errors, and mismatch errors
Solution Approach 1:
The calibration circuit implements a feedback mechanism where the transfer characteristic of the DTC is continuously measured, and correction codes are generated based on the measured deviations. These correction codes are fed back to adjust the DTC operation, compensating for gain errors, integrated non-linearity errors, and mismatch errors, thereby stabilizing the clock signal.
Solution Approach 2:
The calibration system dynamically changes the delay parameters of the DTC based on measured transfer characteristic deviations. By adjusting the delay elements according to correction codes, the system compensates for parameter variations and maintains stable clock signal generation despite manufacturing tolerances and environmental changes.
3Manufacturing precision
If auxiliary delay elements are added for calibration, then the manufacturing precision of the DTC is improved, but the device complexity increases
Solution Approach 1:
The DTC delay elements are segmented into main delay elements and auxiliary delay elements. The main delay elements provide the primary delay function, while the auxiliary delay elements are specifically designed for calibration purposes. This segmentation allows independent optimization of each subset for its specific function, improving overall manufacturing precision.
Solution Approach 2:
The auxiliary delay elements are configured in advance to compensate for specific types of errors (gain errors, integrated non-linearity errors, and mismatch errors). During calibration, these pre-configured elements are activated with correction codes to counteract manufacturing deviations, enabling high precision without requiring all elements to be perfectly manufactured.
Data Source
AI summary
In one example, an apparatus includes a MM divider having a clock input, a first divisor input and a MM divider output; a delta-sigma modulator having a second divisor input, a divisor output and a residual output, the divisor output coupled to the first divisor input; a DTC having a clock input, a control input, a calibration input, and an output, the DTC control input coupled to the residual output, and the DTC clock input coupled to the MM divider output; and a calibration circuit having a first calibration control input, a second calibration control input, and a calibration output, the first calibration control input coupled to the DTC output, the second calibration control input coupled to the residual output, and the calibration output coupled to the DTC calibration input.