Digital-to-Time Converter Using CDAC Charging for PVT Stability

Solution Overview

Problem

Digital-to-time converters (DTCs) are sensitive to process, voltage, and temperature variations, and existing solutions consume power and semiconductor die area, limiting their efficiency and robustness.

Innovation Solution

A capacitive digital-to-analog converter with a common terminal and multiple capacitors, charged by a current source and controlled by a comparator, along with a switched capacitor voltage-to-current converter to generate a stable charging current, reduces power consumption and die area while enhancing robustness to PVT variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a DAC (such as a resistive DAC) is used to convert the digital word into an initial voltage for the charging capacitor, then the DTC can achieve the time delay function, but the DAC consumes power and semiconductor die area

Engineering Contradiction:

Improvetime delay accuracyVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent removes the DAC component from the DTC circuit entirely. Instead of using a DAC to convert the digital word into an initial voltage, the invention directly uses the digital word to control switching elements that connect capacitors to reference voltages, eliminating the need for a separate DAC and its associated power consumption and area

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The capacitors in the circuit serve multiple functions: they store the initial voltage determined by the digital word, and they are subsequently charged by the constant current source to generate the time delay. This multi-functionality eliminates the need for separate components and reduces overall power consumption

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If a DAC (such as a resistive DAC) is used to convert the digital word into an initial voltage for the charging capacitor, then the DTC can achieve the time delay function, but the DAC consumes semiconductor die area

Engineering Contradiction:

Improvetime delay accuracyVSAvoidsemiconductor die area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent removes the DAC component from the DTC circuit entirely. Instead of using a DAC to convert the digital word into an initial voltage, the invention directly uses the digital word to control switching elements that connect capacitors to reference voltages, eliminating the need for a separate DAC and its associated power consumption and area

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The control logic that determines the initial voltage is merged directly into the capacitor switching network. The digital word simultaneously controls both the initial capacitor configuration and the charging process, eliminating the need for a separate DAC and reducing die area

Inventive Principle:

Principle #5Merging (Combining)

3Ease of manufacture

If CMOS delay cells are used to form a DTC, then the circuit can be implemented in standard CMOS technology, but the delay cells are sensitive to process, voltage, and temperature variations

Engineering Contradiction:

ImproveCMOS compatibilityVSAvoidPVT variation robustness

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent replaces the mechanical/physical delay mechanism of CMOS delay cells with an electrical charging process. Instead of relying on the propagation delay through sequential CMOS gates (which is sensitive to PVT variations), the invention uses a capacitor charging process with a constant current source, where the time delay is determined by the capacitor value and current, both of which can be made more stable and less sensitive to process and temperature variations

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution improves power efficiency, reduces semiconductor die area, and enhances stability against process, voltage, and temperature variations, allowing for more integrated circuits in the same space and improved performance in fractional-N PLLs and other applications.

Implementation Method 1

a capacitive digital-to-analog converter including a common terminal and a plurality of capacitors; a first current source configured to charge the plurality of capacitors through the common terminal with a charging current

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

a comparator having a first input terminal coupled to the common terminal

Methodology Applied

Scientific EffectElectrical potential comparison:

Data Source

PatentUS11177819B1Power and area efficient digital-to-time converter with improved stability

Publication Date: 2021.11.16 QUALCOMM INC

AI summary

A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.