DTC Reference Clock Duty Cycle Calibration for Fractional-N PLLs
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Solution Overview
Problem
Digital-to-time converter (DTC)-based fractional-N phase lock loops (PLLs) face challenges in improving in-band phase noise due to reference clock duty cycle errors when the clock rate is doubled, leading to duty cycle errors that disrupt loop dynamics and degrade phase noise performance.
Innovation Solution
A system that includes a clock doubler, a comparator to adjust the reference voltage, and a duty cycle calibration circuit that extracts errors from the comparator output to adjust the clock edge, ensuring accurate duty cycle correction and improving phase noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the reference clock rate is doubled to improve in-band phase noise, then phase noise performance is improved, but duty cycle errors occur which degrade the phase noise performance
Solution Approach 1:
The patent applies preliminary action by performing duty cycle calibration before the PLL lock process. The calibration circuit pre-adjusts the clock edges to compensate for duty cycle errors, ensuring that when the PLL operates at doubled clock rate, the duty cycle errors are already corrected, thus preventing degradation of phase noise performance
Solution Approach 2:
The patent implements feedback through a calibration circuit that monitors the duty cycle of the reference clock and dynamically adjusts the clock edges. The circuit uses the PLL lock signal as feedback to enable calibration only when the PLL is properly locked, ensuring continuous correction of duty cycle errors while maintaining improved phase noise performance
2Manufacturing precision
If duty cycle calibration is performed to correct errors, then duty cycle accuracy is improved, but the convergence time of the PLL is extended
Solution Approach 1:
The patent applies periodic action by performing duty cycle calibration in periodic intervals rather than continuously. The calibration is triggered by the PLL lock signal, occurring periodically when the PLL achieves lock, which balances the need for accurate duty cycle correction with minimizing interruption to the PLL operation and reducing overall convergence time
Solution Approach 2:
The calibration is performed as a preliminary action during the initial PLL lock phase. By completing duty cycle calibration before the PLL enters normal operation, the patent ensures accurate duty cycle correction is achieved upfront, preventing subsequent phase noise degradation without requiring continuous calibration that would extend total convergence time
3Device complexity
If the reference clock duty cycle is not 50%, then clock doubler operation is simplified, but duty cycle errors are introduced that disrupt loop dynamics
Solution Approach 1:
The patent introduces an intermediary calibration circuit between the clock doubler and the PLL loop. This intermediary component detects duty cycle errors from the non-50% duty cycle reference clock and compensates for them by adjusting clock edges, thereby maintaining loop dynamics stability without requiring the reference clock to have exactly 50% duty cycle
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the clock edge timing parameters based on the actual duty cycle of the reference clock. The calibration circuit measures the duty cycle and modifies the clock edge positions to compensate for deviations from 50%, allowing the system to tolerate non-ideal reference clock duty cycles while maintaining stable loop dynamics
Data Source
AI summary
A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.