DTC Clock Generator for Low-Power Multi-Phase Link Timing

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Solution Overview

Problem

High-speed link architectures face issues with increased power consumption and circuit area due to the use of high-frequency reference clocks and complex phase interpolators, which degrade power and area efficiency.

Innovation Solution

Replace phase interpolators with a Digital-to-Time Converter (DTC) to generate local clock signals, utilizing a phase detector and oscillator to synchronize phases and adjust clock signals based on phase error values, reducing power consumption and circuit area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If high-frequency reference clocks are distributed to increase bandwidth, then data transmission capability is improved, but power consumption increases significantly

Engineering Contradiction:

Improvedata transmission capabilityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The invention divides the clock generation function into multiple local clock generators distributed across different lanes. Each local clock generator independently generates clock signals from low-frequency reference clocks, eliminating the need for a single high-frequency reference clock to serve all lanes. This segmentation reduces power consumption while maintaining high data transmission capability across multiple lanes.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If the number of phase interpolators is increased to provide more clock phases, then multi-phase clock generation capability is improved, but device area increases

Engineering Contradiction:

Improvemulti-phase clock generation capabilityVSAvoiddevice area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The invention replaces traditional phase interpolators with a Digital-to-Time Converter (DTC) based approach. Instead of using complex analog phase interpolation circuits that consume significant area, the patent uses digital timing adjustment mechanisms to generate multi-phase clocks from a single-phase reference, dramatically reducing the device area required while maintaining the ability to generate multiple clock phases.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Adaptability or versatility

If phase interpolators are used to generate multi-phase clocks, then clock phase diversity is improved, but power consumption and area efficiency deteriorate

Engineering Contradiction:

Improveclock phase diversityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The invention extracts and removes the phase interpolator component from the clock generation system entirely. By eliminating this power-hungry analog component and replacing it with digital timing adjustment mechanisms, the system achieves clock phase diversity without the associated power consumption penalty, directly addressing the contradiction between phase diversity and power efficiency.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS20260058664A1Clock generator and device including the same

Publication Date: 2026.02.26 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a clock generator including a Digital-to-Time Converter (DTC) configured to output a second reference clock signal by adjusting a phase of a first reference clock signal, an oscillator configured to generate a local clock signal synchronized with an edge of the second reference clock signal, a phase detector configured to generate a phase error value, and a DTC control circuit configured to output a DTC code, wherein, in response to the DTC code matching a bound reference code, the DTC control circuit is configured to update the DTC code to a rollover target code.