Digital-to-Time Converter Current Compensation for Delay Linearity
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Solution Overview
Problem
Digital-to-time converters (DTCs) exhibit non-linearity due to unequal successive input codes specifying respective delays, leading to unacceptable jitter in output signals, particularly in applications like fractional-N phase locked loops.
Innovation Solution
A digital-to-time converter (DTC) design that includes a current-drawing block (CDB) and a correction controller (CC) to ensure a constant total current draw from the power supply, regardless of input code magnitude, using a current digital-to-analog converter (DAC) to complement the variable current component, thereby reducing non-linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If unequal successive input codes are used to specify respective delays in a DTC, then the DTC can operate with variable delay values, but non-linearity is introduced causing unacceptable jitter in output signals
Solution Approach 1:
The patent changes the operating parameters of the DTC by introducing a constant current bias that compensates for the non-linear delay variations caused by unequal successive input codes. This parameter adjustment maintains delay linearity across different input code sequences while preserving variable delay capability.
Solution Approach 2:
The patent implements a feedback mechanism where the actual delay output is monitored and compared against the ideal linear delay, and the error signal is used to adjust the current bias in real-time. This closed-loop control eliminates jitter caused by non-linearity while maintaining the ability to vary delays.
2Productivity
If variable current draw is allowed in the DTC, then the circuit can respond dynamically to different input codes, but power supply ripple increases reducing signal quality
Solution Approach 1:
The patent introduces a counterbalancing current source that generates a current equal in magnitude but opposite in effect to the variable current draw from the power supply. This counter-current compensates for the ripple caused by dynamic current variations, maintaining a stable power supply voltage while preserving dynamic response capability.
Solution Approach 2:
The patent employs an asymmetric current compensation scheme where the bias current is adjusted differently for rising and falling edges of the input signal. This asymmetric adjustment cancels out the periodic ripple components while maintaining the necessary dynamic response to different input codes.
3Device complexity
If simple DTC architecture is used, then device complexity is reduced, but non-linearity correction capability is insufficient
Solution Approach 1:
The patent introduces an intermediary current bias circuit that sits between the power supply and the delay elements. This intermediary component provides the necessary non-linearity correction without requiring fundamental changes to the basic DTC architecture, maintaining simplicity while improving delay accuracy.
Solution Approach 2:
The patent achieves non-linearity correction by adjusting the current parameter flowing through the delay elements rather than changing the structural parameters of the delay circuit itself. This parameter-based correction maintains architectural simplicity while achieving the required delay precision.
Data Source
AI summary
A digital-to-time converter (DTC) of a fractional-n PLL contains a delay generator and a current-drawing block. The current drawn by the delay generator from the power supply contains: (A) a fixed component having a first current magnitude regardless of magnitude of a second code specifying the desired delay; and (B) a variable component having a magnitude determined only by magnitude of the second code. The current-drawing block draws correction-current from the power supply, whose magnitude is determined only by a complement of the second code.