Digital-to-Time Converter Delay Stages for High Linearity
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Solution Overview
Problem
Time-to-digital converters (TDCs) and digital-to-time converters (DTCs) face issues with poor linearity due to mismatches in parasitic resistance and capacitance among components, which affect their resolution and performance, especially in miniaturized designs.
Innovation Solution
The design incorporates a series of delay stages with input and delay circuits, utilizing logic gates to control clock signals and digital control signals, allowing for adjustable activation of delay stages to improve linearity, with each stage contributing to the generation of a delay signal corresponding to a digital control code, and the number of active stages being proportional to the delay range and inversely proportional to linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If miniaturization is pursued for DTCs and TDCs, then device size is reduced, but parasitic resistance and capacitance mismatches worsen, degrading linearity and resolution
Solution Approach 1:
The patent changes the electrical parameters of the delay elements by using current-mode logic circuits where the delay time is controlled by current mirrors rather than voltage switches. This parameter transformation from voltage-based to current-based control reduces the impact of parasitic capacitance and resistance mismatches, thereby maintaining linearity even in miniaturized designs
Solution Approach 2:
The patent replaces traditional voltage-based switching mechanisms with current-mode logic operations. By substituting voltage control with current control in the delay stages, the system becomes less sensitive to parasitic effects, allowing miniaturization without proportional degradation in linearity performance
2Adaptability or versatility
If more delay stages are added to improve delay range, then flexibility increases, but the number of components increases, worsening parasitic mismatches and reducing linearity
Solution Approach 1:
The patent segments the total delay range into multiple coarse delay stages, where each stage provides a fixed delay increment. This segmentation allows the achievement of large delay ranges through combination of stages while keeping each individual stage simple and well-matched, thereby maintaining linearity even with extended delay capability
Solution Approach 2:
The patent implements dynamic control of delay stages through digitally controlled current mirrors that can selectively activate or adjust the current magnitude in each stage. This dynamic adjustment capability allows flexible delay range control while maintaining optimal matching conditions through electronic rather than physical reconfiguration
3Device complexity
If traditional voltage-based switching is used, then design is simpler, but parasitic capacitance effects are stronger, degrading resolution and linearity
Solution Approach 1:
The patent substitutes voltage-based switching with current-mode logic operations throughout the delay stages. Current mirrors provide controlled current sources that are less affected by parasitic capacitance, improving resolution. Although this increases design complexity, the modular current mirror architecture keeps the implementation manageable
Data Source
AI summary
A digital-to-time converter (DTC) includes a plurality of delay stages connected in series, in which each of the plurality of delay stages includes an input circuit and a delay circuit. The input circuit has a first input terminal, a second input terminal and a first output terminal, and is configured to receive a clock signal through the first input terminal, receive a digital control signal through the second input terminal, generate an output signal according to the clock signal and the digital control signal, and output the output signal to the first output terminal of the input circuit. The delay circuit is coupled to the input circuit in series, and is configured to receive the output signal and an input signal, and generate a delay signal according to the output signal and the input signal. The delay signal indicates a time interval corresponding to the digital control signal.