DTC Dithering and Delay Equalization for Spur-Suppressed Clocks
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Solution Overview
Problem
Existing electrical circuits for clock generation face challenges with noise and spurs due to timing mismatches and errors in digital-to-time converters (DTCs).
Innovation Solution
The proposed electrical circuit includes a digital-to-time converter error scrambler to randomize errors and suppress spurs, a background error compensator to mitigate timing mismatches, and a background delay equalizer to calibrate errors such as offset, gain, and integral non-linearity (INL) errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital-to-time converter (DTC) is used for clock generation, then clock frequency control is achieved, but timing mismatches and errors (offset, gain, INL) cause spurs and noise
Solution Approach 1:
The patent applies preliminary calibration actions before normal operation to eliminate timing errors. The background delay equalizer pre-calibrates the DTC by measuring and compensating for offset, gain, and INL errors using calibration signals, ensuring accurate timing before the DTC is used for clock generation, thereby preventing spurs and noise from occurring during operation
Solution Approach 2:
The patent implements feedback mechanisms where the output of the DTC is monitored and fed back to adjust and equalize delay paths. The background delay equalizer uses feedback from timing error detection to continuously adjust and compensate for delay mismatches, maintaining timing accuracy and suppressing spurs and noise through real-time correction
2Productivity
If reference signal injection is used to control oscillator, then clock generation is achieved, but timing mismatch between injection points causes errors
Solution Approach 1:
The patent segments the delay control function into multiple independent delay elements or stages. By dividing the overall delay path into separable segments, the system can individually calibrate and equalize each segment's timing, preventing timing mismatches at injection points while maintaining efficient clock generation through coordinated operation of all segments
Solution Approach 2:
The patent changes the timing parameters of different injection paths to equalize their delays. By adjusting delay values, injection timing, and phase parameters of different signal paths, the system compensates for timing mismatches between injection points, ensuring accurate synchronization without compromising clock generation efficiency
3Stability of the object's composition
If DTC errors are not randomized, then deterministic operation is maintained, but periodic errors generate spurious tones
Solution Approach 1:
The patent applies periodic dithering signals to the DTC control input to randomize periodic errors. By superimposing a small periodic or pseudo-random signal on the deterministic control input, the system converts periodic timing errors into randomized noise, eliminating spurious tones while maintaining overall operational determinism through the dominant control signal
Solution Approach 2:
The patent converts harmful periodic timing errors into beneficial randomized noise through dithering. By intentionally adding controlled randomness to the DTC operation, the system transforms deterministic periodic errors that cause spurs into randomized errors that appear as low-level noise, thereby eliminating spurious tones while maintaining acceptable timing accuracy
Data Source
AI summary
An electrical circuit for clock generation includes a digital-to-time converter error scrambler configured to randomize error in a digital-to-time converter (DTC) and configured to suppress spurs of the electrical circuit, a background error compensator configured to mitigate a timing mismatch between an injection of a reference signal into the DTC at a first point and an injection of the reference signal into the DTC as a second point, and a background delay equalizer configured to calibrate errors of the electrical circuit.