Digital-to-Time Converter Using Dual MMD Interpolation
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Solution Overview
Problem
Existing digital to time converters (DTCs) face limitations in achieving higher output frequencies due to the maximum sampling frequency of frequency dividers, which restricts the maximum output frequency to half of the DTC's input clock, and require complex calibration schemes to mitigate half-frequency spurs, leading to increased area and power consumption.
Innovation Solution
The use of two multi-modulus dividers (MMDs) to generate signals with a minimum division ratio of 1.5, combined through a single interpolation stage, avoiding half-frequency spurs and reducing area and power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency dividers are used for coarse modulation, then the DTC can create the desired signal, but the maximum output frequency is limited to half of the input clock
Solution Approach 1:
The patent segments the frequency division process into multiple stages: a first frequency divider for coarse division, followed by an interpolation stage that further divides the signal. This multi-stage approach allows the output frequency to exceed half the input clock frequency while maintaining timing accuracy, as each stage handles a portion of the total division ratio.
Solution Approach 2:
The patent introduces a time-domain interpolation dimension by inserting intermediate edges between the coarsely divided edges. This adds a temporal dimension to the frequency division process, allowing precise control of output frequency without being constrained by the traditional half-clock limit of single-stage dividers.
2Speed
If the DTC clock is increased to push output frequency higher, then output frequency increases, but timing limitations on the DTC implementation worsen
Solution Approach 1:
The patent employs dynamic interpolation where the interpolation stage adaptively generates intermediate edges based on the desired output frequency. This dynamic approach allows the system to maintain accurate timing relationships across a wide range of output frequencies without requiring a fixed high-speed clock, thereby avoiding timing limitations while achieving higher output frequencies.
3Speed
If frequency doubling is used to achieve higher output frequencies, then output frequency increases, but area and power consumption increase
Solution Approach 1:
The patent merges the frequency division and interpolation functions into a unified multi-stage structure. By combining coarse division and fine interpolation in a single integrated path, the design achieves frequency multiplication effects without requiring separate frequency doubling circuits, thereby reducing the area and power consumption associated with traditional frequency doubling approaches.
4Reliability
If complex calibration schemes are used to mitigate half-frequency spurs, then signal quality improves, but area and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the source of half-frequency spurs by using an odd division ratio in the interpolation stage. This architectural choice inherently prevents the generation of spurious half-frequency components, removing the need for complex calibration schemes and reducing both area and power consumption while maintaining signal quality.
Data Source
AI summary
A digital to time convertor includes a frequency division stage, configured to generate a first frequency output based on a first instruction set and a second frequency output based on a second instruction set; a delay stage, configured to generate a first delayed frequency output and a second delayed frequency output based on the first frequency output, and to generate a third delayed frequency output and a fourth delayed frequency output based on the second frequency output; a selection stage, configured to output one of the first delayed frequency output or the third delayed frequency output based on a control code; and to output one of the second delayed frequency output, the second frequency output, the first frequency output, or the fourth delayed frequency output based on the control code; and a signal generator, configured to generate an interpolated signal based on the output of the selection stage.