DTC Fractional Frequency Synthesis Calibration for Low-Jitter Clocks
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Solution Overview
Problem
Existing frequency synthesizers in SoC devices require significant silicon area due to the large size of LC resonator oscillators, and suffer from electromagnetic coupling issues that degrade spectral purity and jitter.
Innovation Solution
A digital-to-time converter (DTC)-based open-loop frequency synthesis and calibration circuit that uses a high frequency reference clock to drive multiple DTCs, providing a compact, scalable, and low-power solution with reduced EM coupling and improved tuning range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If PLL LC oscillators are used to generate precise clock sources, then frequency accuracy and jitter performance are improved, but silicon area occupied increases significantly
Solution Approach 1:
The patent uses a single PLL LC oscillator as a reference and creates multiple clock sources by copying its output through digital-to-time converters (DTCs) and delay elements. This allows one physical oscillator to serve multiple modules, eliminating the need to duplicate the large LC resonator inductor coil for each clock source while maintaining frequency accuracy and jitter performance.
2Reliability
If multiple PLL LC oscillators are duplicated to provide separate clock sources for multiple modules, then each module gets its own precise clock, but electromagnetic coupling among coils degrades spectral purity and jitter
Solution Approach 1:
The patent extracts the critical frequency generation function from multiple physical oscillators and consolidates it into a single reference PLL LC oscillator. The multiple clock sources are then generated digitally through DTCs and delay elements, separating the analog RF function (confined to one oscillator) from the frequency multiplication and distribution functions. This eliminates electromagnetic coupling between multiple LC resonator coils while maintaining clock source independence for each module.
3Reliability
If multiple PLL LC oscillators are used for multiple modules, then each module has dedicated clock source, but device complexity and power consumption increase
Solution Approach 1:
The patent makes a single PLL LC oscillator serve multiple functions by using its output as a reference for generating multiple different clock frequencies through DTCs and delay elements. This universal reference oscillator approach replaces multiple dedicated oscillators, reducing device complexity and power consumption while maintaining clock source isolation for different modules through digital signal processing.
Data Source
AI summary
A digital-to-time converter (DTC)-based open loop frequency synthesis and calibration circuit may be used to provide a precise clock signal. The DTC calibration circuit may include a DTC to generate a DTC clock signal based on a received input clock frequency and a received initial digital input code, a phase-lock loop (PLL) to generate a PLL clock signal based on a received PLL input, a binary phase-detector (PD) to generate a PD output based on a comparison between the DTC clock signal and the PLL clock signal, a plurality of calibration bins to generate a signed accumulated PD portion based on the PD output, and an adder to generate a calibrated DTC input code based on a combination of the signed accumulated PD portion and a subsequent digital input code, where the DTC generates a calibrated clock signal based on the calibrated DTC input code.