Digital-to-Time Converter Gain Calibration for Low-Jitter Operation
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Solution Overview
Problem
Existing methods for recalibrating the gain of digital-to-time converters (DTCs) during operation are challenging due to low probability of the DTC code being zero, leading to increased jitter and degradation of performance, which is problematic for applications with stringent jitter requirements.
Innovation Solution
A system and method for calibrating DTCs using a calibration DTC and a latch comparator to align output signals, adjusting the calibration DTC code to minimize time differences, and using an average computation module to determine gain errors, allowing calibration at near-zero and near-full code values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing methods are used to recalibrate the DTC's gain during operation when the DTC code is zero, then the gain error can be compensated, but the probability of the DTC code being zero is very low (0.00024 for 12-bit code), making recalibration rare and ineffective
Solution Approach 1:
The patent introduces a calibration DTC that performs calibration actions in advance by generating calibration output signals at near-zero and near-full code values. The digital controller proactively initiates calibration sequences without waiting for the main DTC code to naturally reach zero, ensuring calibration occurs at predetermined opportunities rather than relying on rare natural occurrences.
Solution Approach 2:
The patent introduces a calibration DTC as an intermediary device that facilitates the calibration process. This calibration DTC generates calibration output signals that can be compared with the main DTC output, enabling indirect measurement and adjustment of the main DTC's gain error without requiring the main DTC code to be zero.
2Productivity
If other methods are used to recalibrate the DTC's gain during operation, then the calibration can be performed more frequently, but jitters in the output increase, degrading the DTC's performance
Solution Approach 1:
The patent applies local quality by performing calibration only at specific code regions (near-zero and near-full values) rather than across the entire code range. The calibration DTC is configured to generate calibration output signals only at these specific local conditions, allowing frequent calibration opportunities without the side effects of full-range calibration operations that would increase jitter.
Solution Approach 2:
The patent implements periodic calibration action by having the digital controller initiate calibration sequences at predetermined intervals or when specific code conditions are met. The calibration DTC periodically generates calibration output signals at near-zero and near-full code values, creating regular calibration opportunities that maintain performance without continuous disruption.
3Duration of action of stationary object
If the DTC is operated uninterrupted for several years, then the system maintains continuous operation, but analog impairments (such as gain deviations caused by aging) occur, leading to gain error
Solution Approach 1:
The patent implements feedback by continuously monitoring the relationship between the main DTC output signal and the calibration DTC output signal through a latch comparator. The digital controller receives feedback about gain errors and adjusts the main DTC code accordingly, creating a closed-loop system that automatically compensates for aging effects over extended operation periods.
Solution Approach 2:
The patent enables self-service calibration where the system automatically detects and corrects its own gain errors without external intervention. The digital controller autonomously initiates calibration sequences, compares output signals, determines gain errors, and adjusts the main DTC code based on the calibration results, allowing the system to maintain accuracy throughout its operational lifetime.
Data Source
AI summary
A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.