Online DTC Gain Calibration Using a Comparator Reference Path
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Solution Overview
Problem
Digital-to-time converters (DTCs) in phase lock loop systems and fractional output dividers face challenges in gain calibration during operation due to low probability of zero DTC code occurrence and increased jitter in output, which degrades performance and makes them unsuitable for stringent jitter requirements.
Innovation Solution
A system that includes a first DTC and a calibration DTC, a latch comparator, an average computation module, and a digital controller with a sigma-delta modulator and state machine to align the output clock signal with the calibration output signal by adjusting the calibration DTC code, allowing for frequent calibration without degrading performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional recalibration methods are used when DTC code is zero, then gain error can be compensated, but the probability of calibration event is extremely low (0.00024 for 12-bit code)
Solution Approach 1:
The patent introduces a calibration DTC that performs calibration actions in advance or independently of the main DTC operation. The calibration DTC receives the same clock signal and generates calibration output signals that can be compared with the main DTC output, allowing calibration to occur without waiting for specific DTC code values.
Solution Approach 2:
The patent introduces a latch comparator as an intermediary device that compares the output clock signal from the main DTC with the calibration output signal from the calibration DTC. This comparator generates indication signals that provide feedback about the relative timing, enabling the digital controller to determine gain error without directly observing the main DTC code being zero.
2Reliability
If recalibration is performed during operation, then gain error can be corrected, but output jitter increases which degrades DTC performance
Solution Approach 1:
The patent segments the DTC system into two independent parts: a main DTC that handles normal operation and a calibration DTC that handles calibration functions. Both receive the same clock signal but operate independently, allowing calibration to proceed without interfering with the main DTC's output signal quality.
Solution Approach 2:
The patent applies different functional qualities to different parts of the system. The main DTC is optimized for low-jitter operation during normal service, while the calibration DTC is optimized for generating comparable output signals for calibration purposes. The latch comparator selectively processes only calibration-related timing information.
3Duration of action of stationary object
If the DTC operates uninterrupted for several years, then system availability is maintained, but analog impairments cause gain deviations due to aging
Solution Approach 1:
The patent enables continuous or frequent calibration during DTC operation by using the calibration DTC and latch comparator mechanism. Instead of requiring the system to stop or wait for rare zero-code events, the calibration process can occur continuously in the background, maintaining gain accuracy throughout the extended operational period.
Solution Approach 2:
The patent implements a feedback mechanism where the latch comparator continuously compares the main DTC output with the calibration DTC output and generates indication signals. The digital controller uses these feedback signals to determine gain error and adjust the DTC code accordingly, creating a closed-loop system that maintains accuracy over time despite aging effects.
Data Source
AI summary
A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.