DTC Gain Calibration in Fractional-N PLLs Using Dynamic Reference Voltage
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Solution Overview
Problem
DTC-based fractional-N phase lock loops face challenges in accurately calibrating DTC gain due to voltage and temperature variations, leading to worsened phase noise and spur performance.
Innovation Solution
A voltage generation circuit dynamically adjusts the reference voltage by generating a voltage output based on the difference between a sampled voltage and a reference voltage, ensuring accurate DTC gain calibration and improved PLL performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a fixed DTC gain value is used, then the PLL can operate without calibration, but the phase noise and spur performance deteriorate due to voltage and temperature variations
Solution Approach 1:
The patent implements a feedback mechanism where the PLL output phase is measured and compared against the input phase, and the error signal is used to adjust the DTC gain value dynamically. This closed-loop feedback system continuously compensates for voltage and temperature variations, maintaining accurate DTC gain calibration without requiring manual intervention.
Solution Approach 2:
The patent performs preliminary DTC gain calibration by measuring the PLL output phase and calculating the required gain adjustment before normal operation begins. This preliminary action establishes the correct DTC gain value in advance, ensuring accurate performance from the start of operation without requiring continuous calibration during runtime.
2Measurement precision
If DTC gain calibration is performed continuously to maintain accuracy, then the calibration precision improves, but the convergence time increases
Solution Approach 1:
The patent applies partial calibration action by performing DTC gain calibration only when necessary - specifically, during initial PLL startup and when significant performance degradation is detected. Rather than continuous calibration, the system uses selective partial calibration events, reducing the overall calibration time while maintaining sufficient accuracy for normal operation.
3Measurement precision
If the reference voltage is dynamically adjusted based on voltage and temperature variations, then the DTC gain calibration accuracy improves, but the circuit complexity increases
Solution Approach 1:
The patent makes the voltage generation circuit multi-functional by designing it to serve both as a reference voltage source for the phase detector and as a dynamic calibration element for DTC gain adjustment. This universal circuit performs multiple functions - providing stable reference voltage, enabling phase detection, and facilitating gain calibration - thereby reducing the need for separate dedicated calibration circuits and minimizing overall device complexity.
4Measurement precision
If background calibration is implemented to maintain DTC gain accuracy during PLL operation, then the phase noise performance improves, but the operational complexity increases
Solution Approach 1:
The patent merges the background calibration function with the existing PLL operation by integrating the phase measurement and DTC gain adjustment processes into the normal PLL signal path. The calibration operations are combined with the regular phase detection and control loop functions, allowing calibration to occur during normal operation without requiring separate dedicated calibration hardware or disrupting PLL functionality.
Data Source
AI summary
A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.