DTC Nonlinearity Correction for Low-Jitter ADPLL Timing
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Solution Overview
Problem
Digital-to-Time Converters (DTCs) in Fractional N All Digital Phase Locked Loops (ADPLLs) face challenges in achieving fine resolution while covering multiple cycles of the feedback clock, leading to increased power consumption and design complexity due to the need for a wide time range and high quantization noise.
Innovation Solution
A DTC with a constrained gain calibration loop and integral nonlinearity correction loop is used to reduce the time range the DTC needs to cover by predictively delaying the reference clock, allowing for finer resolution and lower jitter by generating a nonlinearity correction code to normalize the phase difference between the reference and feedback clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the TDC resolution is increased to achieve finer quantization noise, then the measurement precision is improved, but the device complexity and power consumption increase substantially
Solution Approach 1:
The patent divides the TDC functionality into two separate components: a DTC that handles the coarse time delay covering multiple clock cycles, and a TDC that handles fine time measurement with high resolution. This segmentation allows each component to be optimized independently - the DTC can use fewer bits for coarse measurement while the TDC provides fine resolution, avoiding the need for a single high-resolution TDC that would cover the entire time range.
Solution Approach 2:
The DTC acts as an intermediary component between the reference clock and the TDC. It predictively delays the reference clock by a coarse amount based on the accumulated phase error, so that the TDC only needs to measure the remaining fine time difference. This intermediary DTC reduces the measurement range required by the TDC, enabling finer resolution without increasing TDC complexity.
2Measurement precision
If the TDC resolution is increased to reduce quantization noise, then the measurement precision is improved, but the power consumption increases substantially
Solution Approach 1:
By segmenting the time measurement function into DTC (coarse) and TDC (fine), the patent reduces the number of bits required in the TDC. Since power consumption in digital circuits is generally proportional to the number of bits and switching activity, reducing the TDC bit depth from what would be needed for full-range high-resolution measurement directly reduces power consumption while maintaining fine resolution capability.
Solution Approach 2:
The DTC intermediary reduces the measurement burden on the TDC by handling the coarse time delay. This allows the TDC to operate with fewer bits and lower power consumption while still achieving fine resolution for the remaining time difference measurement, as it only needs to resolve small time intervals rather than the full clock cycle range.
3Adaptability or versatility
If the TDC time range is increased to cover multiple feedback clock cycles in FracN PLL, then the adaptability is improved, but the measurement precision deteriorates due to quantization noise
Solution Approach 1:
The patent segments the time measurement task into two parts: the DTC handles the large time range required for FracN PLL operation by delaying the reference clock by multiple cycles, while the TDC handles the fine time measurement with high precision. This segmentation allows the system to accommodate both wide time range and fine resolution requirements that cannot be met by a single TDC.
Solution Approach 2:
The DTC serves as a predictive intermediary that pre-delays the reference clock based on the accumulated phase error from the PLL loop. This predictive action reduces the time range that the TDC must measure, allowing the TDC to maintain fine resolution and low quantization noise even when the overall system must handle multiple clock cycles in FracN mode.
4Measurement precision
If the DTC linearity requirements are made stricter to improve time accuracy, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the TDC measures the actual time difference between the delayed reference clock and the feedback clock, and this measurement is fed back to adjust the DTC control. The DLF (digital loop filter) processes the TDC output and adjusts the DTC control code to minimize the phase error. This feedback loop allows the system to tolerate DTC nonlinearity because the feedback continuously corrects for delays caused by nonlinearity, maintaining time accuracy without requiring the DTC to be highly linear.
Solution Approach 2:
The system uses its own TDC measurement capability to self-correct DTC nonlinearity errors. The TDC measures the actual time delay introduced by the DTC, and this measurement is used to generate correction signals that adjust the DTC control. This self-service mechanism allows the system to compensate for DTC imperfections without requiring external calibration or highly precise DTC design, reducing overall system complexity.
Data Source
AI summary
Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.