DTC-Calibrated PLL Clock Generation for Faster Locking
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Solution Overview
Problem
Existing semiconductor technologies face challenges in quickly deriving the gain value for digital-to-time converter (DTC) circuits, which is crucial for the effective operation of phase locked loop circuits and clock signal generators, particularly in wireless communication devices, leading to prolonged locking times.
Innovation Solution
A clock signal generator and phase locked loop circuit configuration that includes a digital-to-time converter (DTC) and a DTC controller, which determines an initial gain value by comparing delay amounts with the period of previously generated output clock signals, using a binary search algorithm to quickly derive the gain value and calibrate the delay amount, thereby reducing locking time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional methods are used to derive the gain value of the DTC, then the system operates reliably, but the time required to achieve lock state is prolonged
Solution Approach 1:
The patent applies preliminary action by pre-calibrating the DTC gain value through a systematic procedure before normal operation. The DTC controller performs a calibration process that determines the gain value by comparing delay amounts with known time periods (such as clock signal periods) in advance, so that when the PLL needs to lock, the gain value is already prepared and the locking time is significantly reduced.
Solution Approach 2:
The patent employs feedback mechanisms where the DTC controller continuously monitors the delay amount produced by the DTC and compares it with reference values (such as the period of a clock signal). Based on this feedback comparison, the controller adjusts and determines the optimal gain value. This closed-loop feedback ensures both reliability in determining the correct gain value and efficiency in reducing the time required to achieve lock state.
2Measurement precision
If the DTC gain value is determined through extensive calibration, then the delay precision is improved, but the calibration time increases
Solution Approach 1:
The patent applies segmentation by dividing the calibration process into distinct stages or steps. Rather than performing a single extensive calibration, the process is segmented into multiple phases where the gain value is determined through a series of comparisons and adjustments. This segmentation allows for systematic determination of the gain value with adequate precision while managing the total calibration time through structured progression.
Solution Approach 2:
The patent applies partial action by performing just enough calibration to achieve the required precision for normal operation. The calibration process determines the gain value through a controlled number of comparisons and adjustments - not necessarily exhaustive calibration to maximum precision, but sufficient calibration to achieve the precision needed for the PLL to lock reliably. This avoids unnecessary excessive calibration time while maintaining adequate delay precision.
Data Source
AI summary
Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.