DTC Predistortion Calibration for DPLL Linearity and Low Spurious
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Solution Overview
Problem
The implementation of high-performance clock circuits for 6th-generation wireless technology, such as 1024 QAM, is hindered by the nonlinearity issues in Digital Phase Lock Loops (DPLLs), which affect spurious and noise performance, and existing calibration methods are inefficient and sensitive to PVT changes.
Innovation Solution
A linearity calibration method and apparatus for DTC within DPLLs, utilizing a full-digital predistortion approach with higher-order nonlinear functions to adjust the delay of reference and feedback clocks, ensuring they remain in a tracked state, thereby reducing nonlinearity and improving phase synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional phase lock loop is used to produce high quality clock for 1024 QAM, then clock quality requirement is met, but performance bottleneck is hit
Solution Approach 1:
The patent replaces the conventional analog phase lock loop with a digital phase lock loop architecture. The digital DTC (Digital Time Converter) substitutes the analog delay circuit, enabling full-digital implementation that avoids the performance bottlenecks of analog circuits while meeting the stringent clock quality requirements for 1024 QAM modulation.
Solution Approach 2:
The patent introduces a higher-order nonlinear predistortion function (calibration order n≥2) to compensate for DTC nonlinearity. By changing the calibration order from conventional first-order to higher-order, the system achieves better linearity and spurious performance without sacrificing convergence speed, thus resolving the performance bottleneck.
2Adaptability or versatility
If digital phase lock loop is used to replace analog phase lock loop, then design freedom and bandwidth configuration are improved, but nonlinearity issues affect spurious and noise performance
Solution Approach 1:
The patent applies predistortion technique where a higher-order nonlinear function is configured in advance to counteract the expected nonlinearity of the DTC. This preliminary anti-action compensates for the nonlinearity before it affects the phase locking process, thereby reducing spurious and noise performance degradation while maintaining the design freedom of DPLL.
Solution Approach 2:
The patent implements a feedback mechanism where the locked phase error is continuously monitored and fed back to adjust the control word of the DTC. This closed-loop feedback ensures that the system dynamically compensates for nonlinearity effects, maintaining low spurious and noise performance while preserving the adaptability of the digital architecture.
3Ease of manufacture
If existing calibration methods are used for DTC, then implementation is simple, but calibration efficiency is low and sensitivity to PVT changes is high
Solution Approach 1:
The patent performs calibration in advance during the manufacturing process, configuring the higher-order nonlinear predistortion function coefficients before the device is deployed. This preliminary calibration action eliminates the need for complex real-time calibration procedures, maintaining ease of manufacture while dramatically improving calibration efficiency and reducing sensitivity to PVT changes through pre-optimized compensation.
4Manufacturing precision
If higher-order nonlinear predistortion function is used, then linearity and spurious performance are improved, but computational complexity increases
Solution Approach 1:
The patent optimizes the calibration order parameter n to be greater than or equal to 2, balancing the trade-off between linearity improvement and computational complexity. By carefully selecting the appropriate order of the nonlinear function, the system achieves sufficient linearity and spurious performance without excessive computational burden, making the solution practical for implementation.
Data Source
AI summary
The present disclosure provides a linearity calibration method for digital time converter, including: acquiring a phase prediction parameter and a locked phase error, and calculating a control word of a digital time converter according to the phase prediction parameter, the locked phase error, a pre-configured nonlinear predistortion function, and a pre-configured calibration order n, with the control word being configured to enable the digital time converter to adjust a delay of a reference clock, so as to keep the reference clock and a feedback clock which are input to a time digital converter in a tracked state. The present disclosure further provides a linearity calibration apparatus for digital time converter and a digital phase lock loop.