Digital-to-time converter spur reduction via path switching
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Solution Overview
Problem
Digital-to-time converters (DTCs) in radio circuits face significant frequency spurs due to correlated circuit noise being up-converted, which diminishes spurious frequency performance and robustness, particularly in multi-frequency applications where noise-induced spurs are periodic and occur in significant magnitude.
Innovation Solution
Incorporating redundant delay paths within the DTC architecture, where selection logic alternates between different delay paths for specific frequency ramp codes, breaking the periodicity of noise up-conversion and reducing spurious frequency performance by using existing spare components, such as multiplexers and switches, to provide diverse delay paths without significant increments in DTC complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If redundant delay paths are incorporated into the DTC architecture, then spurious frequency noise is reduced by breaking periodicity of noise up-conversion, but device complexity increases due to additional delay paths and selection logic
Solution Approach 1:
The patent applies dynamics by making the delay path selection variable and time-dependent. Instead of a fixed delay path, the system dynamically switches between multiple delay paths based on the frequency ramp code, thereby breaking the periodicity of noise up-conversion and reducing spurious frequency noise.
Solution Approach 2:
The patent segments the delay function into multiple parallel delay paths, each corresponding to different frequency ramp codes. This segmentation allows the system to distribute noise across different paths and reduces the periodicity of noise up-conversion by selecting different segments based on the frequency ramp code.
2Reliability
If multiple delay paths are provided for different frequency ramp codes, then robustness of DTC-based local oscillators is enhanced, but manufacturing complexity increases due to additional circuit components
Solution Approach 1:
The patent applies universality by designing delay paths that serve multiple functions. The same delay path infrastructure is used for different frequency ramp codes, and the selection logic reuses existing multiplexer and switch components. This multi-functionality enhances robustness while minimizing the increase in manufacturing complexity.
3Object-generated harmful factors
If edge jitter is sourced from different circuit components through alternate delay paths, then spurious frequency performance is improved, but device area increases due to additional circuit components
Solution Approach 1:
The patent merges multiple delay paths into a unified structure that shares common components. By combining the delay path infrastructure with existing multiplexer and switch components, the system achieves improved spurious frequency performance without a proportional increase in circuit area.
Data Source
AI summary
This application discusses, among other things, apparatus and methods for improving spurious frequency performance of digital-to-time converters (DTCs). In an example, a method can include receiving a code at selection logic of a digital-to-time converter at a first instant, selecting a first delay path of the DTC to provide a delay associated with the code, associating a second delay path with the code, receiving the code at the selection logic at a second instant, and selecting the second delay path of the DTC to provide the delay associated with the code.