Load-Balanced DTC Timing Path for Deterministic Jitter Compensation
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Solution Overview
Problem
Fractional output dividers (FODs) face challenges in reducing deterministic jitter due to voltage ripple caused by varying settling times during integer and fractional frequency division cycles, which existing technologies fail to adequately address without increasing capacitance or creating supply ripples.
Innovation Solution
A load balancing scheme is implemented, where a load balancing current is sunk during the N+1 phase to equalize current draw, compensating for the extra settling time and ensuring consistent initial conditions, thereby eliminating deterministic jitter without adding large capacitance or creating supply ripples.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fractional output divider uses varying integer division values (N and N+1) for different numbers of cycles to produce fractional frequency, then the output frequency precision is improved, but deterministic jitter increases due to voltage ripple from varying settling times
Solution Approach 1:
The patent applies periodic action by implementing a load balancing circuit that periodically sinks current during specific phases of the N divider operation. This periodic current sinking compensates for the voltage ripple caused by varying settling times when switching between N and N+1 division values, thereby reducing deterministic jitter while maintaining frequency precision
Solution Approach 2:
The patent changes the electrical parameter (current) by introducing a load balancing current that varies based on the division phase. The load balancing circuit sinks current during phases when the N divider operates with N+1 value to compensate for the extra settling time, equalizing the voltage conditions and eliminating deterministic jitter
2Reliability
If large capacitance is added to compensate for voltage ripple, then deterministic jitter is reduced, but device area increases
Solution Approach 1:
The patent substitutes the mechanical/electrical approach of adding large capacitance with an active control approach using a load balancing circuit. Instead of passively compensating for voltage ripple through large capacitors that occupy significant area, the invention actively sinks current in a controlled manner during specific phases, achieving the same jitter reduction effect with minimal area overhead
3Measurement precision
If current draw is varied during different division phases, then frequency division accuracy is improved, but supply voltage stability deteriorates causing supply ripples
Solution Approach 1:
The patent applies the anti-weight principle by introducing a counterbalancing current through the load balancing circuit. This circuit sinks current during specific phases to counterweight the current draw variations caused by switching between N and N+1 division values, thereby stabilizing the supply voltage and preventing ripples while maintaining frequency division accuracy
Data Source
AI summary
In an example, a system includes an N divider coupled to an output of a low dropout regulator. The system also includes a load balancing circuit coupled to the N divider and configured to sink a load balancing current at the output of the low dropout regulator during one or more phases of the N divider. The system includes a switch coupled to the load balancing circuit and configured to connect the load balancing circuit to the output of the low dropout regulator during the one or more phases of the N divider.