Deep Trench Isolation for Noise Interference in Miniaturized Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the era of circuit miniaturization, noise-producing components and noise-sensitive components are often fabricated close together on a wafer, leading to challenges in noise interference, as traditional spacing methods are insufficient to effectively isolate noise.
Innovation Solution
The use of deep trench isolation (DTI) and doping techniques, such as P+ or N+ doping, to create low or high impedance paths between noise-producing and noise-sensitive blocks, with isolation blocks connected to separate grounds to divert noise into an external ground, reducing noise transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If components are spaced out on the circuit board to diminish noise interference, then noise isolation is improved, but circuit miniaturization is limited
Solution Approach 1:
The patent transitions from two-dimensional planar spacing to three-dimensional vertical isolation using deep trench isolation structures. By etching trenches deep into the substrate (through the entire thickness) and filling them with insulating material, noise isolation is achieved in the vertical dimension while maintaining compact horizontal footprint, thus resolving the contradiction between noise isolation and circuit miniaturization.
Solution Approach 2:
The patent segments the substrate into isolated regions using deep trenches that physically divide the circuit into separate blocks. Each block can be independently doped and grounded, creating discrete noise isolation zones. This segmentation allows noise-sensitive and noise-producing components to be placed close together horizontally while maintaining electrical isolation through the trench barriers.
2Object-affected harmful factors
If deep trench isolation is used to isolate blocks, then noise isolation is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple functions into the deep trench isolation structure: (1) physical isolation barrier, (2) electrical grounding path through connected grounds, (3) doping regions for noise sinking, and (4) parasitic capacitance reduction. By merging these functions into a single integrated structure rather than implementing separate components, the patent achieves effective noise isolation while managing device complexity.
Solution Approach 2:
The deep trench isolation acts as an intermediary structure between noise-producing and noise-sensitive blocks. The trench filled with insulating material serves as a mediator that blocks noise transmission paths, while the doping and grounding arrangements provide controlled noise sinks. This intermediary approach isolates the two functional blocks without requiring complete physical separation.
3Productivity
If blocks are placed close together for miniaturization, then circuit integration is improved, but noise interference increases
Solution Approach 1:
The patent applies different doping levels and grounding arrangements to specific local regions around noise-producing components. By creating locally optimized isolation zones with appropriate doping concentrations and grounding configurations, the patent enables high circuit integration density while controlling noise generation and transmission at critical locations where components are placed close together.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively isolates noise between blocks, reducing parasitic capacitance and impedance, thereby protecting noise-sensitive components from noise interference and improving overall circuit performance.
Implementation Method 1
a first block of the wafer and a second block of the wafer isolated from the first block using a first deep trench isolation (DTI). The device further includes a third block of the wafer isolated from the second block using a second DTI
Implementation Method 2
The first vertical section and the second vertical section are either P+ or N+ doped to provide a low resistance path to noise from the first block
Implementation Method 3
The second vertical section is doped lightly compared to the first vertical section and the second vertical section
Data Source
AI summary
A device fabricated on a wafer is disclosed. The device includes a first block of the wafer and a second block of the wafer isolated from the first block using a first deep trench isolation (DTI). The device further includes a third block of the wafer isolated from the second block using a second DTI. The second block includes a first vertical section coupled to a first ground, a second vertical section, a third vertical section coupled to a second ground. The second vertical section is doped lightly compared to the first vertical section and the second vertical section.