Semiconductor Device With Deep Trench Isolation Capacitor
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Solution Overview
Problem
Semiconductor devices face challenges in minimizing chip area while requiring high capacitance and high voltage-rated decoupling capacitors, as existing solutions lead to increased surface area and complexity with multiple decoupling capacitors.
Innovation Solution
The implementation of a Deep Trench Isolation (DTI) structure forms a three-dimensional parallel plate capacitor, where the dielectric plates extend perpendicular to the substrate, allowing for increased capacitance and voltage rating without expanding the surface area, by segmenting the semiconductor layer with trenches and using the DTI as a dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MIM capacitors are used to achieve high capacitance and high voltage rating, then the capacitor performance is improved, but the chip area becomes much larger
Solution Approach 1:
The patent transitions from planar capacitors to three-dimensional stacked capacitors by extending capacitor structures vertically through multiple layers. The first and second capacitors are stacked in the vertical direction with shared electrode structures, enabling high capacitance and voltage rating without increasing chip area. This dimensional change allows capacitor plates to extend in the depth direction rather than spreading horizontally.
2Reliability
If multiple decoupling capacitors are formed to stabilize voltage in power supply lines, then voltage stability is improved, but the number of capacitors and chip area increase
Solution Approach 1:
The patent merges multiple capacitor functions into a compact stacked structure where the first and second capacitors share common electrode structures and insulating layers. This consolidation provides multiple decoupling capacitances for voltage stabilization while reducing the total number of discrete capacitor components and their interconnections, thereby lowering device complexity.
Solution Approach 2:
The patent implements a nested capacitor structure where the second capacitor is formed within the same vertical space as the first capacitor by sharing electrode structures. The second capacitor's electrode is positioned between the first capacitor's electrode and the substrate, creating a nested arrangement that maximizes capacitance density without increasing chip area or component count.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of capacitors with high capacitance and high voltage ratings in a small area, efficiently utilizing chip space and allowing for multiple capacitors to be formed within the element isolation region, thereby optimizing chip area utilization.
Implementation Method 1
The DTI structure is utilized to form a three-dimensional parallel plate capacitor
Implementation Method 2
an insulator is formed in the trench... the DTI as a dielectric layer
Data Source
AI summary
According to one embodiment, the semiconductor device with element isolation by DTI has a layer of the first electroconductive type formed on a substrate. The semiconductor layer of the second electroconductive type is formed on the embedding layer. The first DTI has the following structure: a trench is formed from the surface of the semiconductor layer through the first layer into the substrate and surrounds the semiconductor layer, and an insulator is formed in the trench. The second DTI is formed around the periphery of the semiconductor layer. The first electrode is connected to the first region of the semiconductor layer divided by the first DTI. The second electrode is connected to the second region of the semiconductor layer divided as mentioned previously. The first region and the second region form electrode plates and the first DTI forms the dielectric, to thereby form a capacitor.