Discrete-Time Linear Equalizer Using Switched-Capacitor Taps
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Solution Overview
Problem
Continuous-time analog front-ends (CT-AFEs) in high-speed serial data receivers face challenges in realizing circuit functions due to conflicting constraints of power, linearity, noise, and substrate area, especially with increasing data rates and decreasing power supply voltages, leading to non-linear compression and linear distortion, particularly in PAM-4 signaling.
Innovation Solution
Implementing a discrete-time analog front-end (DT-AFE) with discrete-time linear equalizer (DTLE) and discrete-time programmable gain amplifier (DT-PGA) circuits, which operate in the discrete-time domain to reduce ADC dynamic range requirements and mitigate inter-symbol interference (ISI) through feed-forward equalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If continuous-time analog front-end (CT-AFE) is used to equalize received data signal and drive ADC, then signal quality can be maintained, but power consumption increases and linearity deteriorates due to non-linear compression and linear distortion
Solution Approach 1:
The patent transforms the continuous-time equalizer into a discrete-time equalizer by changing the temporal domain parameter. The DTLE uses switched-capacitor circuits that operate in discrete time intervals, fundamentally altering the operating parameters to achieve lower power consumption while maintaining equalization functionality. This parameter transformation allows the circuit to avoid the continuous power consumption inherent in CT-AFE designs.
Solution Approach 2:
The patent replaces the continuous-time analog circuitry with discrete-time switched-capacitor circuits. The mechanical analogy involves replacing continuous operation with discrete switching events, where clock-driven switches control capacitor charging and discharging to achieve equalization. This substitution eliminates the need for continuous analog processing, thereby reducing power consumption.
2Measurement precision
If continuous-time analog front-end (CT-AFE) is used to equalize received data signal, then signal quality can be maintained, but substrate area increases
Solution Approach 1:
The patent changes the temporal operating parameter from continuous to discrete, enabling the use of switched-capacitor techniques that consume less substrate area. The discrete-time operation allows for more efficient resource utilization and reduced circuit footprint compared to continuous-time implementations.
Solution Approach 2:
The patent combines multiple functions into the discrete-time linear equalizer circuit, including signal sampling, holding, and equalization operations. By merging these functions into a unified discrete-time architecture, the overall substrate area is reduced compared to separate continuous-time circuits.
3Speed
If continuous-time analog front-end (CT-AFE) is used with increasing data rates and decreasing power supply voltages, then high-speed transmission can be achieved, but circuit function realization becomes increasingly difficult due to conflicting constraints
Solution Approach 1:
The patent changes the fundamental operating parameter from continuous-time to discrete-time, which simplifies circuit design for high data rates. The discrete-time approach with switched-capacitor circuits is better suited for modern CMOS technologies operating at lower supply voltages, as it provides more predictable behavior and easier control at high speeds.
Solution Approach 2:
The patent introduces clock-driven dynamic operation to the equalizer circuit, allowing it to adapt to varying data rates. The switched-capacitor implementation provides dynamic control through clock signals, enabling the circuit to function effectively at high speeds where static continuous-time circuits would fail due to voltage and timing constraints.
4Measurement precision
If discrete-time linear equalizer (DTLE) is used to mitigate inter-symbol interference (ISI), then signal quality improves, but circuit complexity increases
Solution Approach 1:
The patent replaces complex continuous-time analog equalization circuits with discrete-time switched-capacitor circuits. The substitution of continuous operation with discrete switching events simplifies the circuit implementation while achieving the same ISI mitigation function. The clock-driven switching mechanism provides precise control with simpler hardware.
Data Source
AI summary
An apparatus comprises a discrete-time linear equalizer circuit. The discrete-time linear equalizer circuit includes a sample and hold circuitry including multiple switched-capacitor circuits. The multiple switched-capacitor circuits include at least a switched-capacitor circuit of a pre-cursor tap, a switched-capacitor circuit of a cursor tap, and a switched-capacitor circuit of a post-cursor tap. A clock-driven switch circuitry is to switchably couple a capacitor of the switched-capacitor circuit of the pre-cursor tap to a negative signal input over a first time period, a capacitor of the switched-capacitor circuit of the cursor tap to a positive signal input over a second time period, and a capacitor of the switched-capacitor circuit of the post-cursor tap to the negative signal input over a third time period. The clock-driven switch circuitry is to switchably couple the capacitors of the switched-capacitor circuits in parallel over a fourth time period.