DTMOS Transistor Body-Gate Connection via Hydrogen Cleavage
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Solution Overview
Problem
Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) devices face challenges in maintaining high threshold voltage like Complementary Metal-Oxide Semiconductor (CMOS) devices, leading to reduced power consumption and heat dissipation, but existing methods do not effectively address the dynamic nature of the threshold voltage.
Innovation Solution
The process involves forming P-well and N-well regions in a semiconductor substrate, implanting hydrogen to create a hydrogen-concentrated layer, and then cleaving the wafer to separate the regions, allowing the body of the DTMOS transistors to be connected to the gate, thereby dynamically adjusting the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the body of DTMOS devices is connected to the gate to reduce threshold voltage, then power consumption is reduced, but the threshold voltage becomes dynamically changing and difficult to control
Solution Approach 1:
The patent segments the semiconductor substrate into separate P-well and N-well regions that are physically isolated from each other through cleavage. This segmentation allows independent control and stabilization of threshold voltages in P-type and N-type MOS devices, resolving the instability caused by the dynamic body-gate connection while maintaining low power consumption benefits.
Solution Approach 2:
The patent introduces hydrogen as an intermediary element by implanting it to create a hydrogen-concentrated layer at the interface between P-well and N-well regions. This hydrogen layer acts as a mediator that stabilizes the threshold voltage by controlling charge distribution at the well-region interface, enabling stable threshold voltage while maintaining the body-gate connection for low power operation.
2Loss of energy
If ultra-low power supply voltage is used to reduce power consumption, then battery weight and heat dissipation are reduced, but device performance and reliability may deteriorate
Solution Approach 1:
The patent changes the physical and chemical parameters of the semiconductor structure by implanting hydrogen to create a hydrogen-concentrated layer. This parameter change stabilizes the threshold voltage and improves device reliability, allowing ultra-low power supply voltages to be used without sacrificing performance or reliability.
Solution Approach 2:
The patent performs preliminary hydrogen implantation and wafer cleavage before device fabrication and operation. This preliminary action creates a stable structural foundation with controlled charge distribution, ensuring device reliability is established before the devices are operated at ultra-low power voltages.
3Device complexity
If P-well and N-well regions are formed in the same substrate to create DTMOS devices, then device integration is achieved, but parasitic capacitance increases and chip area is consumed
Solution Approach 1:
The patent physically segments the P-well and N-well regions by cleaving the wafer into separate portions. This segmentation eliminates the parasitic capacitance between adjacent P-well and N-well regions that would exist in integrated structures, while still achieving device integration through the shared hydrogen-concentrated layer and coordinated fabrication process.
Solution Approach 2:
The patent extracts the P-well and N-well regions from a single integrated substrate structure by cleaving them into separate wafers. This extraction removes the harmful parasitic capacitance between the well regions while maintaining the benefits of having both P-type and N-type devices in the overall system through separate but coordinated processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and heat dissipation in portable electronic devices by enabling the use of ultra-low power supply voltages while minimizing parasitic capacitance and optimizing chip area usage.
Implementation Method 1
implanting hydrogen to create a hydrogen-concentrated layer
Data Source
AI summary
A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. The DTMOS transistor includes a gate electrode, and a source/drain region adjacent to the gate electrode. The source/drain region is disposed in the well region. A well pickup region is in the well region, and the well pickup region is at a back side of the semiconductor substrate. The well pickup region is electrically connected to the gate electrode.