Distributed Unit PHY Transfer Functions for Deterministic 5G Processing

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Solution Overview

Problem

5G wireless systems face challenges in performing real-time physical layer processing efficiently due to non-deterministic latency and high power consumption on commercial-off-the-shelf hardware, necessitating hardware accelerators that are costly and hinder resource pooling.

Innovation Solution

Implement transfer functions to perform physical layer operations in distributed units, combining multiple sequential signal processing modules without separate reading and buffering, reducing processing time and resource intensity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If commercial-off-the-shelf hardware is used for real-time processing, then cost is reduced and resource pooling becomes possible, but processing latency becomes non-deterministic and extra processing latency must be added to compensate

Engineering Contradiction:
ImprovecostVSAvoidprocessing latency determinism
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the physical layer processing into distinct functional modules (channel coding, modulation, MIMO processing, etc.) that can be independently executed. This modular segmentation allows COTS hardware to process different segments in a coordinated manner, reducing the impact of non-deterministic latency in any single segment while maintaining overall real-time performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by pre-processing data blocks before transmission to COTS hardware, organizing them in a format optimized for sequential processing. This preliminary organization reduces the computational burden during real-time execution, allowing COTS hardware to meet deterministic latency requirements without requiring specialized accelerator cards.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If hardware accelerators are used for intensive real-time computations, then processing speed and reliability are improved, but cost increases and resource pooling benefits are negated

Engineering Contradiction:
Improveprocessing speedVSAvoidcost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent merges multiple sequential signal processing modules into unified processing pipelines that can be efficiently executed on COTS hardware. By combining functions such as channel coding, modulation, and MIMO processing into integrated software modules, the system achieves hardware-accelerator-level performance on general-purpose processors, eliminating the need for costly specialized hardware while maintaining high processing speed.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent ensures continuity of useful action by implementing overlapping processing windows where data blocks are processed in a continuous stream rather than discrete batches. This continuous processing approach maximizes CPU utilization and maintains high throughput on COTS hardware, matching the productivity of hardware accelerators without the associated cost.

Inventive Principle:
Principle #20Continuity of useful action

3Adaptability or versatility

If multiple sequential signal processing modules are used with separate reading and buffering, then processing flexibility is improved, but processing time and resource intensity increase

Engineering Contradiction:
Improveprocessing flexibilityVSAvoidprocessing time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent applies the nested doll principle by implementing nested data structures where inner data blocks are processed within outer processing windows. This nesting allows multiple levels of processing to occur simultaneously, with inner loops handling specific signal processing functions while outer loops manage overall data flow. This approach maintains processing flexibility through configurable processing levels while reducing total processing time by eliminating redundant buffering operations between sequential modules.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS12500800B2Real time physical layer processing in distributed units
Publication Date: 2025.12.16 OUTDOOR WIRELESS NETWORKS LLC
  • US12500800B2 patent drawing
  • US12500800B2 patent drawing
  • US12500800B2 patent drawing

AI summary

The present disclosure describes methods and apparatus for real-time physical layer processing in distributed units (DU). A downlink data processing method includes receiving a downlink transport block at the physical layer and generating a plurality of sub-transport blocks mapped to a plurality of symbols by processing the received transport block. The method further includes processing the plurality of sub-transport blocks sequentially using at least one transfer function to generate the plurality of symbols which are then transmitted to a radio unit (RU) for transmission to a user equipment (UE). An uplink data processing method includes generating an uplink transport block by processing a plurality of symbols received at the DU from the RU. The plurality of symbols are processed using at least one uplink transfer function. A downlink/uplink transfer function is functionally equivalent to a plurality of downlink/uplink sequential signal processing modules.