Dual-Active Layer Thin Film Transistor for High Resolution Displays
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Solution Overview
Problem
The increasing demand for higher display resolution in display devices requires shorter charging times for pixel electrodes, which existing thin film transistors cannot efficiently achieve due to longer charging times with larger numbers of pixel units.
Innovation Solution
A thin film transistor design with upper and lower active layers, sources, and drains, connected via holes, and insulation layers, allowing simultaneous charging of pixel electrodes through two paths, enhancing charging capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixel units is increased to improve display resolution, then the display quality is improved, but the charging time becomes longer
Solution Approach 1:
The thin film transistor is divided into two independent charging paths: an upper path with upper source, upper active layer, and upper drain, and a lower path with lower source, lower active layer, and lower drain. This segmentation allows simultaneous charging through multiple parallel paths, effectively doubling the charging capacity and reducing charging time while maintaining the ability to support high-resolution displays with numerous pixel units
2Productivity
If the charging capability of thin film transistor is improved to reduce charging time, then the display effect is improved, but the device complexity increases
Solution Approach 1:
The upper and lower charging paths are merged into a single thin film transistor structure that shares a common gate electrode and is integrated within the same pixel unit. This merging approach doubles the charging capability while avoiding the complexity of completely separate transistor structures, as the upper and lower paths are coordinated through the shared gate control
Data Source
AI summary
The embodiments of the present invention provide a thin film transistor including a gate, an upper active layer, a lower active layer, an upper source, a lower source, an upper drain and a lower drain. The upper active layer and the lower active layer are disposed at an upper side and a lower side of the gate, respectively, the lower source and the lower drain are connected to the lower active layer, respectively, and the upper source and the upper drain are connected to the upper active layer, respectively. The embodiments of the present invention also provide an array substrate including the thin film transistor, a method of fabricating the array substrate, and a display device including the array substrate.