Dual-ADC Clocking for High-Order Frequency Measurement

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Solution Overview

Problem

Current delta-sigma A/D converters face challenges in measuring high-order frequencies beyond the fifth order, as they require increased sampling frequencies, leading to higher consumption currents and chip die sizes, making them non-compliant with international standards like R46 of OIML for frequencies up to the 40th order.

Innovation Solution

A semiconductor device with a clock controller that supplies a first clock signal for electric power measurement and a second, higher sampling frequency for high-order frequency measurement, allowing the device to perform high-order frequency measurement without significantly increasing consumption currents and chip die sizes by using a delta-sigma A/D converter for electric power and a SAR A/D converter for high-order frequencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a single delta-sigma A/D converter operates at high sampling frequency (235 kHz) to measure 40th-order frequency signals, then high-order frequency measurement capability is achieved, but consumption current and chip die size greatly increase

Engineering Contradiction:
Improvehigh-order frequency measurement capabilityVSAvoidconsumption current
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent divides the measurement function into two separate A/D converters: a delta-sigma A/D converter for electric power measurement at low sampling frequency (3.9 kHz) and a SAR A/D converter for high-order frequency measurement at high sampling frequency (235 kHz). This segmentation allows each converter to operate at its optimal frequency, achieving 40th-order frequency measurement capability without requiring the delta-sigma converter to run at high frequencies, thus avoiding excessive current consumption.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If a single delta-sigma A/D converter operates at high sampling frequency (235 kHz) to measure 40th-order frequency signals, then high-order frequency measurement capability is achieved, but chip die size greatly increases

Engineering Contradiction:
Improvehigh-order frequency measurement capabilityVSAvoidchip die size
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent segments the measurement functions into two specialized converters. The delta-sigma A/D converter maintains its low-frequency operation for power measurement, while the SAR A/D converter handles high-frequency sampling for 40th-order frequency analysis. This functional segmentation prevents the need to scale up a single converter's operating frequency, thereby controlling chip die size while achieving the required measurement capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements multi-functionality by enabling the semiconductor device to perform both electric power measurement and high-order frequency measurement (up to 40th order) using two specialized A/D converters working in parallel. The delta-sigma converter handles power measurement at 3.9 kHz while the SAR converter handles frequency measurement at 235 kHz, allowing the system to meet multiple measurement requirements simultaneously without excessive resource consumption.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If the sampling frequency is increased from 3.9 kHz to 235 kHz for the delta-sigma A/D converter, then 40th-order frequency measurement is enabled, but the device complexity increases

Engineering Contradiction:
Improvefrequency measurement orderVSAvoidconverter configuration complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the signal processing tasks into two distinct conversion paths. The delta-sigma A/D converter is dedicated to electric power measurement at low sampling frequency, while the SAR A/D converter is dedicated to high-order frequency measurement at high sampling frequency. This segmentation avoids the complexity of configuring a single converter to handle both low-frequency power measurement and high-frequency spectral analysis simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent achieves multi-functionality by integrating two different types of A/D converters that can operate independently at their optimal frequencies. The system can simultaneously perform electric power measurement and 40th-order frequency measurement without requiring complex configuration of a single converter, as each converter type is optimized for its specific measurement domain.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10267834B2Semiconductor device and measuring method
Publication Date: 2019.04.23 RENESAS ELECTRONICS CORP
  • US10267834B2 patent drawing
  • US10267834B2 patent drawing
  • US10267834B2 patent drawing

AI summary

There is a need for high-order frequency measurement without greatly increasing consumption currents and chip die sizes. A semiconductor device includes: an electric power measuring portion that performs electric power measurement; a high-order frequency measuring portion that performs high-order frequency measurement; and a clock controller that supplies an electric power measuring portion with a first clock signal at a first sampling frequency and supplies a high-order frequency measuring portion with a second clock signal at a second sampling frequency. The second sampling frequency is higher than the first sampling frequency.