Randomized Dual-ADC Sampling to Eliminate Video Stripe Artifacts

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Solution Overview

Problem

Modern digital television systems face calibration challenges due to hardware limitations, resulting in noticeable 'stripes' on images caused by offsets between analog-to-digital converters (ADCs) when multiple ADCs are used for fast signal conversion.

Innovation Solution

A dual channel sampling method and system that employs a random generation scheme for interleaving sampling sequences, using a reference clock generator and a clock controller to dynamically modify the sampling clock signal, ensuring each frame or line of pixels has a unique sampling order, thereby minimizing detectable patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple ADCs are used to increase sampling speed, then productivity is improved, but manufacturing precision deteriorates due to offset between ADCs causing visible stripes

Engineering Contradiction:
Improvesampling speedVSAvoidimage quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies dynamics by making the sampling sequence random rather than fixed. The system dynamically changes the sampling order between different ADCs using a random number generator, so that no two consecutive frames use the same sampling sequence. This dynamic approach prevents the formation of visible stripe patterns while maintaining high sampling speed through multiple ADCs.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of sampling sequence from fixed to random. By generating random control values that determine the sampling order of different ADCs, the system transforms the static sampling pattern into a variable one, thereby eliminating the repetitive stripe artifacts while preserving the high productivity gained from using multiple ADCs.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If fixed interleaving sequence is used for simplicity, then device complexity is reduced, but object-generated harmful factors increase due to noticeable stripe patterns

Engineering Contradiction:
Improvesampling sequence controlVSAvoidstripe patterns
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent converts the potential harm of added complexity (random sequence generation) into a benefit by eliminating the more harmful stripe patterns. The random number generator and clock controller add complexity to the sampling sequence control, but this complexity directly prevents the generation of visible stripe artifacts, thus converting the harm of complexity into the benefit of improved image quality.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Object-generated harmful factors

If random interleaving sequence is implemented to eliminate patterns, then object-generated harmful factors are reduced, but device complexity increases due to random signal generator and clock controller

Engineering Contradiction:
Improvevisible stripesVSAvoidsampling sequence control
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent introduces intermediary components (random number generator and clock controller) that mediate between the fixed ADCs and the sampling process. These intermediaries generate random sequences that control the sampling order, thereby eliminating visible stripes without requiring fundamental changes to the ADC hardware architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7777660B2Multi-channel sampling system and method
Publication Date: 2010.08.17 MEDIATEK INC
  • US7777660B2 patent drawing
  • US7777660B2 patent drawing
  • US7777660B2 patent drawing

AI summary

An apparatus and method for sampling a plurality of digital video signals to generate an interleaved digital video signal is disclosed. The apparatus includes: a first analog-to-digital converter (ADC), coupled to an analog input signal, for converting the analog input signal to a first digital output signal according to a sampling clock signal; a second ADC, coupled to the analog input signal, for converting the analog input signal to a second digital output signal according to the sampling clock signal; a reference clock generator, for generating a reference clock; a random signal generator, for outputting control values in a random sequence; and a clock controller, coupled to the reference clock generator and the random signal generator, for modifying the reference clock signal according to the control values to generate the sampling clock signal to the first ADC and the second ADC.