Dual Address Decoding in Distributed Shared Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current distributed shared memory (DSM) systems face challenges in maintaining address space consistency when memories are decommissioned, faulted, or altered, requiring cumbersome updates to all system address decoders, which limits flexibility and scalability.
Innovation Solution
Implementing a multi-level address decoding scheme where local system address decoders handle initial decoding, and a network switch performs secondary decoding, allowing updates to be isolated to local and switch-based decoders, reducing the need for global updates and enhancing flexibility and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If every system address decoder is updated to reflect changes in memory structure, then memory access requests are routed properly and faults are reduced, but the system experiences unwanted downtime and the update process is cumbersome and tedious
Solution Approach 1:
The patent divides the address decoding function into two segments: local address decoders at each node and a remote address decoder at the network switch. This segmentation allows updates to be performed locally without requiring system-wide coordination, thereby reducing downtime while maintaining proper memory access routing through the hierarchical decoding structure.
2Reliability
If every system address decoder is updated to reflect changes in memory structure, then memory access requests are routed properly, but the update process becomes cumbersome and tedious
Solution Approach 1:
By segmenting the address decoding into local and remote components, the patent simplifies the update process. Local decoders only need to be updated at individual nodes, while the remote decoder at the switch handles the comprehensive memory structure information, making updates less cumbersome and more manageable.
Solution Approach 2:
The remote address decoder at the network switch acts as an intermediary that centralizes the management of memory structure information. This intermediary handles the complex task of tracking memory changes and provides updated routing information to local decoders, simplifying the overall update process.
3Adaptability or versatility
If a multi-level address decoding scheme is implemented with local and switch-based decoders, then updates are isolated to local and switch-based decoders reducing the need for global updates, but the device complexity increases
Solution Approach 1:
The patent implements segmentation of the address decoder into local and remote components, which increases adaptability by allowing independent updates at different levels. The increased device complexity is justified by the significant improvement in system flexibility and the ability to perform memory structure changes without global coordination.
Solution Approach 2:
The patent adds a new dimension to the address decoding architecture by introducing a hierarchical structure with local and remote decoders operating at different levels. This dimensional change enables greater flexibility in memory structure changes while distributing the complexity across multiple components rather than concentrating it in a single global decoder.
Data Source
AI summary
Generally discussed herein are systems, devices, and methods for local and remote dual address decoding. According to an example a node can include one or more processors to generate a first memory request, the first memory request including a first address and a node identification, a caching agent coupled to the one or more processors, the caching agent to determine that the first address is homed to a remote node remote to the local node, a network interface controller (NIC) coupled to the caching agent, the NIC to produce a second memory request based on the first memory request, and the one or more processors further to receive a response to the second memory request, the response generated by a switch coupled to the NIC, the switch includes a remote system address decoder to determine a node identification to which the second memory request is homed.