Dual Address Maps for Memory Bandwidth and Synchronization
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Solution Overview
Problem
Fine-grain distributed cache memory architectures in computing systems lead to significant performance reduction due to lengthy memory synchronization operations, which are inefficient and burdensome for processors.
Innovation Solution
Implementing a method that allows a computing system to concurrently use a fine-grain distributed address map for high-bandwidth access and a source-ordered non-distributed address map for memory synchronization, maintaining synchronization and coherency without software intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If fine-grain distributed address map is used for high-bandwidth memory access, then memory bandwidth is improved, but memory synchronization performance deteriorates due to lengthy synchronization operations across multiple L2 slices
Solution Approach 1:
The patent segments the address map into two distinct types: a fine-grain distributed address map for high-bandwidth access and a source-ordered non-distributed address map for synchronized access. This segmentation allows each address map type to serve its specific purpose optimally without interfering with the other, resolving the contradiction between bandwidth and synchronization performance
Solution Approach 2:
The patent applies different quality characteristics to different parts of the memory access system. The fine-grain distributed address map provides high bandwidth for memory accesses that don't require strict ordering, while the source-ordered non-distributed address map provides strong ordering guarantees for synchronization-critical accesses. Each address map type has locally optimized properties suited to its specific use case
2Speed
If fine-grain distributed address map is used to achieve high memory bandwidth, then memory access speed is improved, but processor performance is reduced due to significant delay in memory synchronization operations
Solution Approach 1:
The patent segments memory access paths into two distinct routes: one through the fine-grain distributed address map for high-speed access, and another through the source-ordered non-distributed address map for synchronized access. This segmentation enables the system to achieve high processor performance by using the appropriate access path for different workloads without being penalized by the other path's characteristics
Solution Approach 2:
The patent introduces an intermediary mechanism in the memory controller that automatically selects between the two address map types based on the memory access requirements. This intermediary layer resolves the contradiction by mediating between the desire for high speed and the need for synchronization, directing traffic to the appropriate path without requiring software intervention
3Reliability
If memory synchronization operation is issued to ensure data visibility, then memory coherence is improved, but time consumption increases due to synchronization across multiple L2 slices taking thousands to tens of thousands of processor clock cycles
Solution Approach 1:
The patent segments synchronization operations into two distinct pathways: those using the fine-grain distributed address map that require coordination across multiple L2 slices (taking thousands to tens of thousands of cycles), and those using the source-ordered non-distributed address map that maintain ordering without requiring wide-ranging synchronization. This segmentation allows the system to achieve memory coherence with minimal time loss by utilizing the appropriate path
Solution Approach 2:
The patent extracts the synchronization requirement from the fine-grain distributed address map path and places it in a separate source-ordered non-distributed address map path. By taking out the synchronization function from the high-speed path, the system eliminates the time loss associated with synchronizing across multiple L2 slices while maintaining coherence where needed
Data Source
AI summary
Various embodiments include techniques for performing memory operations in a computing system. A processing unit in the computing system performs memory operations by accessing memory using two concurrent memory address maps (AMAPs). The processing unit access memory via a first fine-grain distributed AMAP in order to access memory with high-bandwidth without imposing strict ordering of memory operations. The processing unit access memory via a second AMAP source-ordered non-distributed AMAP in order to access memory where memory synchronization latency is more important than memory bandwidth. By accessing memory via the two concurrent AMAPs, the processing unit can select between high-bandwidth memory access and source-ordered memory access interchangeably, depending on which is desired for each memory operation. Further, the fine-grain distributed AMAP and the source-ordered non-distributed AMAP can maintain synchronization and coherency between one another concurrently without software intervention, thereby alleviating the burden on the application programmer to manage the two AMAPs.