Dual Address Generation for Irregular Memory Access Circuits
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently performing irregular and continuous memory accesses required for multi-standard and multi-channel wireless communication systems, leading to increased circuit size and processing load, particularly due to the need for large conversion tables and complex address conversion patterns.
Innovation Solution
A semiconductor device with a first address generation unit that generates a table address using a cyclically repeating pattern and a second address generation unit that generates an access address based on parameter information, allowing for non-continuous access addresses that repeat in a long cycle, thereby reducing the size of the table memory and processing load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conversion tables are used to perform irregular and continuous memory accesses, then address conversion capability is improved, but circuit size increases due to large table memory requirements
Solution Approach 1:
The patent segments the address conversion process into multiple stages: a first address generation unit generates base addresses using cyclic patterns, while a second address generation unit generates offset addresses. This segmentation eliminates the need for large conversion tables by dividing the address space into manageable segments that can be generated algorithmically.
Solution Approach 2:
The patent employs periodic cyclic patterns in address generation where the first address generation unit uses a cyclically repeating first pattern and the second address generation unit uses a cyclically repeating second pattern. This periodic action allows the system to generate non-continuous access addresses with long cycles using minimal table information, dramatically reducing circuit size while maintaining address conversion capability.
2Productivity
If complex address conversion patterns are implemented, then irregular memory access efficiency is improved, but processing load increases
Solution Approach 1:
The patent reduces processing load by replacing complex address conversion algorithms with periodic cyclic patterns. The first and second address generation units generate addresses using simple cyclically repeating patterns, which are computationally efficient and can be implemented with minimal processing resources while still achieving the required irregular memory access patterns.
Solution Approach 2:
The address generation units are self-sufficient in generating addresses through their internal cyclic patterns without requiring complex external control logic or large conversion tables. The system serves itself by generating the necessary address sequences through the interaction of the two simple cyclic pattern generators, reducing overall processing complexity.
Data Source
AI summary
A semiconductor device according to the present invention includes a first address generation unit that includes a first register group and generates a table address by a cyclically repeating first pattern using a value stored to the first register group, a second address generation unit that includes a second register group and generates an access address by a cyclically repeating second pattern using a value stored to the second register group and parameter information determined by the table address, and a control unit that outputs setting information to be supplied to the first register group and the second register group. Further, the semiconductor device performs at least one of a read process and a write process of data from and to a data memory using the access address.