Semiconductor Contact and Bit Line Layout With Dual Air Gaps
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Solution Overview
Problem
As the integration level of semiconductor devices increases, the decreasing distance between conductive structures leads to increased parasitic capacitance, resulting in poor performance of semiconductor devices. Additionally, forming air gaps that are either too wide or too narrow poses challenges in sealing and contour uniformity.
Innovation Solution
A forming method for a semiconductor structure that involves forming two layers of air gaps: a first air gap on the sidewalls of the bit line structures and a second air gap on the sidewalls of the contact plugs. This method improves the reduction of parasitic capacitance and facilitates easier sealing of the air gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between conductive structures is decreased to increase integration level, then the integration level is improved, but the parasitic capacitance between conductive structures increases
Solution Approach 1:
An air gap structure is introduced as an intermediary between adjacent bit line structures. This air gap acts as a dielectric medium with lower permittivity than conventional dielectric materials, thereby reducing the parasitic capacitance between conductive structures while maintaining their close proximity for high integration density
Solution Approach 2:
The permittivity parameter of the dielectric material between conductive structures is changed by replacing conventional high-k dielectric materials with air (effectively zero-k). This parameter change directly reduces the capacitance value C = kε₀A/d, allowing closer spacing of bit lines without proportionally increasing parasitic capacitance
2Device complexity
If a single layer of air gap is formed, then the structure is simple, but the sealing difficulty increases and contour uniformity deteriorates
Solution Approach 1:
The air gap structure is segmented into two distinct layers: a first air gap layer and a second air gap layer. This segmentation allows each layer to be optimized independently for specific functions - the first layer provides primary capacitance reduction while the second layer enhances sealing and maintains contour uniformity, solving the reliability issues of single-layer designs
Solution Approach 2:
The two air gap layers are nested within each other in a hierarchical structure, with the first air gap and second air gap positioned at different vertical levels. This nested configuration allows the inner layer to provide one function (capacitance reduction) while the outer layer provides another function (sealing and uniformity), achieving multiple benefits simultaneously
Data Source
AI summary
A forming method for a semiconductor structure and the semiconductor structure are provided. The forming method of the semiconductor structure includes: providing a substrate, wherein separate bit line structures are formed on the substrate; forming a first sacrificial layer on a sidewall of a bit line structure; forming first dielectric layer filling gaps between adjacent bit line structures; patterning a first dielectric layer to form vias, wherein the vias expose active regions of the substrate, and the vias and remaining parts of the first dielectric layers are alternately arranged in an extension direction of the bit line structures; forming a second sacrificial layer on sidewalls of a via, and filling the via to form a contact plugs; forming a contact structure on the contact plug; and removing the first sacrificial layer to form first air gap, and removing the second sacrificial layer to form a second air gap.