Dual-Array Memory with Symmetric Read Current Profile
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Solution Overview
Problem
Existing memory technologies, such as SRAM, face security vulnerabilities due to asymmetric current consumption patterns when reading '0' and '1' bits, allowing hackers to potentially infer stored data by monitoring power supply current profiles.
Innovation Solution
Implementing a dual-memory array architecture with a main and auxiliary array, where both arrays are read simultaneously to produce symmetric current profiles, and using a twist circuit with a random number generator to randomly swap signal inputs to sense amplifiers, making it difficult to distinguish between read bits based on current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single memory array is used for data storage, then the device complexity is low, but the security against electrical probing attacks is compromised due to asymmetric current profiles
Solution Approach 1:
The memory is divided into two separate arrays: a first array storing main data and a second array storing complement data. This segmentation allows the system to read both arrays simultaneously and combine their current profiles, creating a symmetric overall profile that prevents information leakage through electrical probing while maintaining the security benefit of complementary storage.
2Reliability
If dual memory arrays with simultaneous reading are implemented, then symmetric current profiles are achieved for security, but the device complexity increases
Solution Approach 1:
The read circuits of the first and second arrays are merged into a shared read path with a common sense amplifier. Both arrays are read simultaneously and their bit line currents are combined at the sense amplifier stage. This merging approach achieves symmetric current profiles for security while reducing overall complexity compared to having completely separate read paths for each array.
3Reliability
If complement data is stored in the second array, then security is enhanced through symmetric profiles, but the manufacturing precision requirements increase
Solution Approach 1:
Both the first and second arrays are designed with identical bit cell structures, transistor configurations, and interconnect layouts to create equipotential conditions. This symmetry in design ensures that both arrays have matching current profiles under identical operating conditions, which is essential for achieving the security benefit of symmetric overall current consumption during read operations.
Data Source
AI summary
Memories are provided. A memory includes a first memory array, a second memory array and a read circuit. The first memory array is configured to store first data. The second memory array is configured to store second data that is complementary to the first data. The read circuit includes a decoding circuit, a sensing circuit and an output buffer. The decoding circuit is configured to provide a first signal according to the first data and a second signal according to the second data in response to an address signal. The sensing circuit is configured to provide a first sensing signal according to a reference signal and the first signal, and a second sensing signal according to the reference signal and the second signal. The output buffer is configured to provide the first sensing signal or the second sensing signal as an output according to a control signal.